资源列表
[VHDL编程] 4x2_priorityencoder
说明:verilog code for priority encoder<sandeep> 在 2025-06-09 上传 | 大小:7kb | 下载:0
[VHDL编程] DIANZIRILI
说明:EDA 用VHDL语言做的电子万年历,有全套的代码还有仿真-EDA using VHDL language to the electronic calendar, there is a full set of code there are simulation<cleool> 在 2025-06-09 上传 | 大小:7.81mb | 下载:0
[VHDL编程] XilinxFPGA1.1
说明:十分钟学会Xilinx FPGA 设计浅显易懂的学习书,为FPGA的初学者提供很好的参考-10 minutes Society of Xilinx FPGA design easy to understand book learning, for FPGA to provide a good reference for beginners<郭子> 在 2025-06-09 上传 | 大小:1.66mb | 下载:0
[VHDL编程] Springer_2006_SystemVerilog_for_Verificatio_Chris
说明:A Guide to Learning the Testbench System Verilog Language Features<aj000> 在 2025-06-09 上传 | 大小:1.35mb | 下载:0
[VHDL编程] Writing_Testbenches_using_System_Verilog
说明:Testbench creation and development methodology with System Verilog. By Janick Bergeron.<aj000> 在 2025-06-09 上传 | 大小:2.64mb | 下载:0
[VHDL编程] fifo_32_4321
说明:用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit,输出数据可以配置为4-1任意bit。有设计文件和testbench-Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench<keven> 在 2025-06-09 上传 | 大小:5kb | 下载:0
[VHDL编程] edacounter
说明:用VHDL语言编写的计数器,在板子上运行成功,可以循环计数,加减计数,先置数后计数等-Counter with the VHDL language, in the board to run successfully, you can cycle counting, addition and subtraction counting, numbers, counting the first home<fana> 在 2025-06-09 上传 | 大小:1.02mb | 下载:0