搜索资源列表
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Dist
FPGA-implementation-of-CORDIC
- 就目前的趋势来看，对硬件复杂信号处理的了解主要是缺少对硬件信号处理结构的了解。虽然有许多硬件高效算法的存在，但是由于在过去得25年里软件的优势明显，人们对这些法则并不了解。CORDIC法则就是其中的一个，它是运用平移-相加完成某些三角函数，双曲线，线性，对数的运算功能。虽然有很多的文章已经介绍了CORDIC 运算法则的各种不同的方面 ，却很少有针对CORDIC在FPGA上执行的研究。这篇论文就是研究在一个CORDIC体系下，以往的那些功
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system cl
DBounce
- Using mechanical switches for a user interface is a ubiquitous practice. However, when these switches are actuated, the contacts often rebound, or bounce, off one another before settling into a stable state. Several meth
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modificatio
xapp514
- Audio/Video Connectivity Solutions for Virtex-IIPro and Virtex-4 FPGAs xapp514_latest.之前网站上有一个，但是不是最新的，缺少一些程序，比如xapp514_asrc.zip。这个是最新的版本。-xapp514 Audio/Video Connectivity Solutions for Virtex-IIPro and Virtex-4
FFT-Using-FPGAs-(2)
- FPGA IMPLEMENTATION OF FPGA
FM_Transmitter
- This the MATLAB for the DSP working behind FM transmitters in FPGAs etc.-This is the MATLAB for the DSP working behind FM transmitters in FPGAs etc.
sha1-progect
- Xilinx XC2VP20 FPGAs. The complete SHA-1 chip Verilog source
usbconnchip-proj
- Xilinx XC2VP20 FPGAs USB interface sources - Xilinx XC2VP20 FPGAs USB interface sources
VGADISPLAY
- 这是一个在FPGA平台下对VGA显示的操作，已经在FPGA开发板上测试通过。-This is an example about VGA display in FPGAS platform,it is tested in the FPGA development board.
TVout
- TV Output for Xilinx FPGAs
VHDL-Lab1
- It is a good programming tech to design fpgas and ICs.
vga
- vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown,
AdcInterfaces
- A VHDL Code for ADC Interfaces in FPGAs
xilinx_intc
- Interrupt controller driver for Xilinx Virtex FPGAs.
i2c_master
- This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller
FPGA-design-and-verification-using-Simulink
- Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ability to function
Design-for-Embedded
- Design for Embedded Image Processing on FPGAs ，FPGA图像处理算法-Design for Embedded Image Processing on FPGAs