搜索资源列表
GEN_HDMI
- 基于XILINX SOC的HDMI配置的SDK工程和IP核，用于HDMI芯片的配置-XILINX SOC based on the HDMI configuration SDK engineering and IP cores for HDMI chip configuration
hdmi_xps
- 基于XILINX SOC的HDMI配置最小系统IP核和SDK工程，用于进行HDMI芯片的配置-Configuring an HDMI chip XILINX SOC minimum system configuration of HDMI IP core and SDK works for
TFT-LCD
- 基于Nios+II的LCD驱动IP核的设计,IP核altera tft lcd controller -Design of the Nios+II driver IP core based on LCD, IP core TFT LCD controller Altera
songer
- 自带IP核的音乐播放器，代码齐全，包括分频、滤波等子模块-IP core comes with a music player, the code is complete, including dividing and filtering sub-module
W7100A
- 带IP核的单片机W7100A的底层驱动代码，一些基础网络通信协议，包括套接字等。-With IP core of single chip microcomputer W7100A underlying driver code, some basic network communication protocols, including socket, etc.
QuartusII_IP_Core
- 以设计双端口RAM为例说明QuartusII中利用免费IP核的设计的详细教程-To design dual-port RAM as an example of the use of a detailed tutorial QuartusII free IP core design
my_second_fpga
- 用Quartus ii13.0写的二进制加法器，使用了IP核RAM，以及LCD显示，打开就能直接使用。-Using Quartus ii13.0 write binary adder, using the IP core RAM, and LCD display, open can be used directly.
fifo_mem
- 同步FIFO，IP核生成ram，已验证可用。-Synchronous FIFO, IP core generation ram, verified available.
CoreUartTest
- Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 har
pwm
- 自定义pwm ip核，符合AVALON总线-Custom PWM IP core, in line with the avalon bus
ethernet_tri_mode
- FPGA 10M/100M/1000M以太网IP核源码，外接88e1111phy芯片进行了仿真验证，对FPGA 以太网MAC层开发人员非常有用-The FPGA 10 m/100 m/1000 m Ethernet IP core source code, an external 88 e1111phy chip simulation verification, is very useful for developers FPGA Et
i2c_master_controller
- Verilig语言描述的I2C Mater控制器的IP核，已经过实践应用，适合于FPGA I2C接口设计应用。本IP核在Altera QII 15.1软件环境下综合，并且包含基于NiosII Gen2处理器的i2c软件驱动代码。-Verilig language I2C Mater described controller IP core, has been the practical application, suitable for
qam16-TX
- 基于Altera MAX10 FPGA的QAM16发送端设计代码，其中采用了MAX10 Fir滤波器IP核。供相关设计人员参考，或者进一步咨询本人。-Based on Altera MAX10 FPGA design of QAM16 the sender code, which uses the MAX10 Fir filter IP core. Related reference for designers, or further
fft
- 基于fpga的fft变换，用ip核实现。用vhdl编写-Fpga based fft transform, use ip core implementation. Written in vhdl
cf-fft
- 用ip核实现fft。用vhdl编写。altera的fpga-Ip core implementation using fft. Written in vhdl
fft_streaming
- 关于QuartusII FFT ip核的使用，采用Streaming模式，包含Modelsim仿真程序-About QuartusII FFT ip nuclear use, using Streaming mode, including Modelsim simulation program
CanIPCore
- microblaze软核生成，外设包括IO、timer及can总线控制芯片SJA1000自定义IP核-Soft MicroBlaze generation, including IO, timer and can peripheral bus control chip SJA1000 custom IP core
asyn_fifo2
- 采用Verilog语言，使用FPGA内部IP核FIFO模块，实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
PLL
- 采用Verilog语言，使用IP核的PLL，产生3种不同频率的输出，已测试验证通过-Using Verilog language, the use of IP cores PLL, produces three kinds of output at different frequencies, it has been verified by test
ADS523x
- ADI 高速ADC芯片ADS523x 的Avalon IP核-the ADI high speed ADC chip ADS523x s Avalon IP core