搜索资源列表
three-vhdl
- VHDL下实现3分频率波形,完整源代码,学习参考-VHDL under three frequency waveform, complete source code, study reference
DigitalClockVHDL
- 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
38encode
- 三八译码器的源代码，在quartus II 6.0中进行进行设计的，有vhdl源代码-March 8 decoder source code, in quartus II 6.0 for the design, Source code is vhdl
abcdefghijk
- 这是一个数字密码锁的VHDL源代码 花了很多时间才弄来的-This a digital code lock VHDL source code spent a lot of time obtained
ocidec3_IDE_controller
- 硬盘控制器VHDL源代码，实现了PIO和DMA方式，请支持-hard disk controller VHDL source code and realized the PIO and DMA mode, please support
FIR_beh
- FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
GetRomData
- 生成4种方式的DDS输出的读表程序的VHDL源代码程序。-four ways generation of DDS output of the meter reading procedures VHDL source code procedures.
yangwenli
- 计费器设计中速度控制模块、里程计数模块、计费计数模块vhdl源代码-accounting device design speed control module, the mileage counter module, billing module count vhdl source code
Uart2
- uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.
DJDPLJ_T
- 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to ac
wave
- 波形发生器的vhdl源代码，6个通道同步-Waveform generator of the VHDL source code, six-channel synchronization
qqq
- 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
Intel_Flash
- intel flash控制器VHDL 源代码-intel flash controller VHDL source code
VHDL-timer
- 这是关于VHDL时钟的源代码，欢迎大家下载交流！-This is a clock on the VHDL source code, welcomed the exchange of everyone to download!
des
- DES加密VHDL源代码,包括速度优先与面积优先两种设计-DES encrypted VHDL source code, including the rate of priority and an area of priority two design
ip_fft128
- 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
DDS
- DDS的VHDL源代码，是数字QPSK调制解调中的重要组成部分。-DDS of the VHDL source code, the number of QPSK modulation and demodulation is an important part.
sdram_inf
- sdram操作的vhdl源代码，对自己编写SDRAM核有很好的参考意义-SDRAM operation of VHDL source code, the preparation of their own nuclear SDRAM have a good reference value
6-portRegisterFile
- 6端口寄存器IP内核VHDL源代码，所需的开发环境是QUARTUS II 6.0。-6-port register IP core VHDL source code, required for the development environment is QUARTUS II 6.0.
VGAcontrol
- alter控制VGA输出VHDL源代码 使用方法： 1.拷贝到硬盘，用Quartus中新建工程，添加文件即可。-alter control VGA output VHDL source code to use: 1. copy to your hard disk, using Quartus in new construction, you can add files.