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Virtex5-datasheet-
- VIRTEX开发必须的中文文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX development must the Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
Virtex5user-guide
- VIRTEX用户文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX development must the Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
xilinx-forHDLDesigns
- VIRTEX原语库文件的中文文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX primitives library file Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
xilinx-forSchematicDesigns
- VIRTEX原理图原语库文件的中文文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX schematic primitives library file Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
PipelineCPU
- 设计一个32位流水线MIPS微处理器，具体要求如下： 1. 至少运行下列MIPS32指令。 ①算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令：SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。
GenesysGeneral-ucf
- Genesys™ Virtex-5 FPGA Development Board用户约束文件，来自官方LX50T板子-Genesys™ Virtex-5 FPGA Development Board Genesys--VIP GenesysGeneral-ucf.zip
ddrpspsbf
- 基于FPGA的雷达脉冲预分选器设计--这里, 提出一种基于关联比较器的雷达信 号分选方法,在实现多参数分选的同时, 也保证了实时性。详细阐述了在 Virtex 4 系列 FPGA 上实现基于内容可寻存储器 ( CAM)的关联比较器的途径。-Design of Radar Pulse Signal Pre-sorting Based on FPGA
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modificatio
1-D-DWT_verilog-code
- Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT fo
Xilinx_PCIe_Core-DMA
- 本文档介绍了一种基于Xilinx Endpoint Block Plus PCIe IP Core，由板卡主动发起的DMA设计。该设计利用通用的LocalLink 接口，所以方便的兼容支持Xilinx PCIe 硬核的器件，例如Virtex 5，Virtex 6，Spartan 6，并且实际在ML555 和ML605 开发板上实际测试通过。此外，驱动将板卡的控制封装起来，提供用户层简单的读写接口，方便上层程序的开发。-This docu
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virte
ConvCodeXilinx
- This a convolutional encoder in xilinx virtex-5 ML506 board FPGA. This program use matlab for comunicating with FPGA. The convolutional encoder using rate 1/2, and 1/3.The register are 3,4,5,6 and 7.-This is a convolutio
xapp514
- Audio/Video Connectivity Solutions for Virtex-IIPro and Virtex-4 FPGAs xapp514_latest.之前网站上有一个，但是不是最新的，缺少一些程序，比如xapp514_asrc.zip。这个是最新的版本。-xapp514 Audio/Video Connectivity Solutions for Virtex-IIPro and Virtex-4
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performan
example_design
- 基于Xilinx最新的Virtex-7的存储器IP核的使用，verilog语言编写的所有源码。-Based on Xilinx latest Virtex-7 FPGA,all of the MIG IP code sources by Verilog language.
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the em
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
lcd_test1
- 基于xilinx ISE的microblaze模块完成的流水灯程序，芯片为virtex-5-Program of water-led which is based on xilinx ISE microblaze.The cell is virtex-5.
eetop.cn_Product_Selection_Guide
- Virtex-6 FPGA Configuration
wenbenxianshi
- 用modelsim和ise开发文本显示系统。包括键盘PS2输入，SVGA视频同步，RGB处理，作者姓名显示，光标发生，图片动态显示。采用XUP Virtex-II Pro开发系统。-With modelsim and ise development text display system.Including the PS2 keyboard input, SVGA video synchronization, RGB, author n