搜索资源列表
NATW06fpga
- Resources in Virtex-4 FPGAs
AdcClock
- Device: Virtex-6 -- Author: Marc Defossez -- Entity Name: AdcClock -- Purpose: High-speed local clock control for an interface between a FPGA and a -- Texas Instruments ADC. -- Tools: ISE - XST -- Lim
AdcData
- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcDataMultiChnl -- Purpose: Four channel version of the data capturing for a Texas Instruments ADC -- Tools: ISE, XST -- Limitations: none -- -- Re
AdcFrame
- -- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcFrm -- Purpose: This file is part of an FPGA interface for a Texas Instruments ADC. -- Tools: ISE + XST -- Limitations: none--- Device: Virtex-5
AdcMem
- -- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcMem -- Purpose: Clock crossing data buffer made from distributed memory. -- Tools: -- Limitations: none--- Device: Virtex-5 -- Author: Marc Defo
AdcToplevel
- -- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcToplevel -- Purpose: FPGA interface to a Texas Instruments ADC -- Tools: ISE, XST -- Limitations: none--- Device: Virtex-5 -- Author: Marc Defos
KCPSM3_V6_29Mar10
- KCPSM3 with Virtex-6 Devices here the user have JTAG_Loader_6 Version v6.0 for uploading the program to the MCU memory without re-synthesis.
Perl_for_CRC
- Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic.
xapp957
- The system provides an example of how to integrate the Virtex-5 Embedded Tri-Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board and a PC-base
SDI_PassThru_VHDL_Virtex5_ise12_2
- SDI_PassThru_VHDL是针对Virtex5 LXT FPGA的SDI码流从GTP收端环出到发端的一个完整工程，源自于Xilinx提供的源码，不一样的是去掉了开发板ml571所要求的昂贵的收发时钟同步子板，经过长时间的调试后，终端电视仍然可以显示，但是会丢帧。（收发时钟不同步，丢帧和收不到SDI码流都是正常的）-SDI_PassThru_VHDL for SDI application in the Virtex 5 FPGA
i2c_1.tar
- i2c driver for video decoder ad9980 in virtex
Virtex-Analog-to-Digital-Converter
- adc verilog 很不错的，希望对大家有所帮组-adc verilog
xapp224datarecovery
- Data recovery allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts the data from the incoming clock/data stream and then moves this data into a separate clock d
based-on-Xilinx-PCIe-Core-DMA
- 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据
vga-and-keyboard
- VGA AND KEYBOARD INTERFACING WITH VIRTEX 4
S2C_-Dual_Virtex-6_Manual
- S2C Xilinx Virtex-6原型验证板手册-S2C Xilinx Virtex-6 Manual
11_170_1
- Xilinx的FPGA的PCIe的VHDL代码，已经验证。-Xilinx FPGA Virtex-5 PCie
XFPGA_DDR_SDRi
- 基于Xilinx FPGA的DDRSDRAM的Verilogg控制代码，使用的FPGA为Virtex. -Based on Xilinx FPGA' s DDRSDRAM Verilogg control code, the use of FPGA as the Virtex.
ds112
- xilinx Virtex-4简介 三个系列 - LX/SX/FX - Virtex-4 LX：高性能逻辑应用解决方案 - Virtex-4 SX：高性能数字信号处理 (DSP) 应用解决方案 - Virtex-4 FX：高性能全功能嵌入式平台应用解决方案-Virtex-4 Family Overview
qpsk_demod_use_FPGA
- 根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能