搜索资源列表
S05_example_Network
- vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)
PDM2PCM.srcs
- use verilog to trans PDM to PCM signal,use vivado
fpg
- vivado file for ram test.
AM调制解调
- 基于Artix-7 FPGA的AM调制解调代码，从AD读入信号后，进行AM调制，并解调输出（将代码分成两个工程就是AM的调制和解调），其中解调用到的数字滤波采用MATLAB设计(The AM modulation and demodulation code based on artix-7 FPGA, after reading the signal from AD, carries out AM modulation, and dem
sram_ctr
- SRAM VERILOG 实现FPGA控制SRAM的功能。测试可以使用。(SRAM verilog fpga vivado ise quartus.)
lab6
- 使用vivado和Xilinx开发板实现VGA图像显示，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)
lab7
- 使用vivado和Xilinx开发板实现蓝牙远程控制，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize Bluetooth remote control, the development board is Xilinx artix-7)
581371_H.264verilog
- H264编码 verilog vivado(H264encoder verilog vivado)
Project05_LwIP
- Vivado v2018.3 LWIP ZYNQ project
Comparative study of FFA architectures using different multiplier and adder topologies
- Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly.