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mult88
- 两个8*8矩阵相乘，每个矩阵内部元素相同，简化运算；modelsim编译仿真，ise或vivado下载，实现FPGA显示。(Two 8*8 matrix multiplication, each element of the same matrix, simplifying the operation; Modelsim compiler simulation, ISE or vivado download, to achieve FP
lab1
- Verilog lab1 is used for learning vivado
gate_test
- 使用vivado hls 对GATE代码进行封装，主要调试stream接口(using vivado hls to archieve GATE syn, to debug the AXI4-stream interface)
LAB2
- zynq上实现流水灯的软硬件协同设计，利用vivado 2015.2版本eda软件开发。(Zynq realizes the design of hardware and software of water lamp, and uses vivado version 2015.2 EDA software to develop it.)
PUB
- 使用xlilnx的vivado为基础环境开发的示波器，采用串口屏显示图像(Using xlilnx vivado based environment development oscilloscope, using serial display images)
ps_bram
- 通过ZYNQ的PS部分读写片上BRAM存储器(Read and write on-chip BRAM memory via the PS portion of the ZYNQ)
mem_wr
- 通过ZYNQ的PS部分读写DDR3存储器(Read and write the DDR3 memory via the PS portion of the ZYNQ)
DigitalFrequencyMeter
- 使用Basys3开发板，采用等精度测频方法实现信号的测频并通过LCD1602显示。(The use of Basys3 development board, the use of equal precision frequency measurement method to achieve signal frequency measurement, and through the LCD1602 display.)
sim_Xilinx综合与仿真设计指导
- Xilinx自己出的仿真设计指导，使用vivado工具必备参考资料。(The Synthesis and Simulation Design Guide provides a general overview of designing Field Programmable Gate Array devices using a Hardware Descr iption language. It includes design hints
src
- 用于国密4的加解密算法实现，采用verilog 语言，可进行vivado仿真，vivado版本是2013，结果经测试正常，适合从事相关行业的工作人员进行借鉴和开发。(The code is realized and simulated by verilog. The simulation result has been confirmed by the author. It is recommended to download by t
ug897-vivado-sysgen-user
- FPGA和matlab关联用到的文档，很有帮助，大家可以学习一下(FPGA and matlab associated with the document, very helpful, we can learn about it)
hf_mot
- 电机驱动及编码器同步采样，内部兼具多重滤波采样处理算法。(Motor drive and encoder synchronous sampling, the internal multi filter sampling and processing algorithm.)
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
project_1
- 在FPGA上实现一个流水灯，包括端口设定等(On FPGA to achieve a water led, including port settings)
project_2
- simple gates using ip integrator from xilinx
ps_ps_test
- 跑马灯，在vivado平台模拟，zybo开发板实现(Water lights, simulations in vivado platform, zybo development board implementation)
clock
- 一个简单的24h时钟,包含开机、关机、暂停、置数功能，以及整点时脉冲响五次(a simple digital clock implemented on Vivado)
Xilinx新一代FPGA设计套件Vivado配套资料
- verilog经典教程，入门者的必选书籍，非常实用，可以学习到很多的知识(verilog classic tutorial, entry must be books, very practical, you can learn a lot of knowledge)
temp
- 掌握时间一直是人们最基本的需求，而在快节奏的当今社会，时间更是一个很重要的工具。电子时钟是利用电子技术构成时钟功能的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，拥有更长的寿命，因此现在越来越得到广泛的使用。按照系统设计功能的要求，系统分为综合计时模块，数据调整模块，红外接收解码模块以及显示模块等4个模块，其中综合计时模块又包含7个子模块（年、月、日、星期、时、分、秒），每个子模块都具有预置，计数和进位的功能。(Time
prova_ped
- project for test in PED currently going through the course