搜索资源列表
FFT
- FFT的经典实现，三重循环的蝶形运算，适合于硬件实现的软件版本，在Xilinx的Vivado仿真器下编译通过-Classic implementation of FFT software version is suitable for hardware implementation in Xilinx Vivado emulator compiled by
lic_Xilinx_ISE_Vivado
- 这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用-Xilinx ISE 14.x vivado, vivado_hls license, pro-test available
Canny
- 首先利用C实现了一个图像边缘提取的算法，然后利用vivado高层次综合，将其综合为verilog代码。-First, the use of C implements a image edge extraction algorithm, then use vivado high-level synthesis, as its comprehensive verilog code.
Xilinx
- XILINX大讲堂、十招加速Vivado IPI设计、Vivado HLS 中指针作为top 函数参数的处理、Vivado HLS 中的浮点设计编码风格与技巧、编写高效Vivado HLS 工程testbench 的三个要素-XILINX auditorium, ten strokes accelerate Vivado IPI design, Vivado HLS deal with top pointer as function p
ac701-pcie-rdf0225-2013.2-c
- 赛灵思7系列开发板ac701，PCIE参考设计，VHDL/Verilog，开发环境Vivado-xilinx 7 series design Kit AC701 PCIe reference design. VHDL/Verilog, design environment Vivado
fft
- vivado hls编写的八点fft工程，代码简洁清晰有注释，C语言编写-Vivado HLS written FFT engineering at eight o clock, the code is concise and clear with comments, C language
zedboard_CTT_v2013_2_130807
- 在文档里包含有Xilinx公司的软件Vivado的实验教程，可以尽快的对zedboard有个深入的学习了解，有助于初学者的快速学习-In a document containing the Xilinx Vivado experimental tutorial software, you can as soon as possible to have a depth of zedboard learn about, to help be
ipi_example_design_2013.1
- ipi example design for vivado 2013.1
Xilinx
- vivado 14.2 crack,can be used -vivado 14.2 crack
ug947-vivado-partial-reconfiguration-tutorial(1).
- tcl partial reconfig synthesis code
bit2dec_fft
- bit to dec 并对数据进行FFT变换，配合xilinx Vivado采数使用。-and the data bit to dec FFT transform, with the number of use xilinx Vivado mining.
hdl-master
- AD9361的ip核，已经调试通过，在vivado上可以运行通。AD9361是一个双通道的便捷收发器，通常用于3G/4G基站。-AD9361' s ip nuclear, debugging has been passed on vivado can run through. AD9361 is a dual-channel transceiver convenient, usually used in 3G/4G base st
xapp1082-zynq-eth
- PS and PL Ethernet Performance and Jumbo fr a me Support with PL Ethernet in the Zynq-7000 AP SoC 是学习Vivado 入门文档，源自xilinx，权威易懂 -PS and PL Ethernet Performance and Jumbo fr a me Support with PL Ethernet in the Zynq-7
yuv422tobt1120
- yuv422转bt1120时序，vivado工程，用tpg做信号源-yuv422 to bt1120
rs232
- 使用VHDL语言在vivado平台上编的串口通信的完整工程，并能用EGO1开发板成功验证(The complete project of serial communication is compiled on the vivado platform using VHDL language, and it can be successfully verified with the EGO1 development board.)
demodulation
- 基于verilog HDL的BPSK解调的FPGA实现，仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
Xilinx
- 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G E
vivado2018+IPs
- Xilinx Vivado 2018 License File
ddr3
- ALINX7010 ddr3读写测试仿真实验官方教程 附说明和代码 Vivado 实现(Alinx7010 DDR3 read write test simulation experiment official course Descr iption and code attached Vivado implementation)
vivado2018+IPs
- licence vivado 2018.3