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test_5.0_tetris
- 基于Vivado实验平台，用Verilog语言编写的俄罗斯方块，可以在FPGA硬件上上下载运行(Based on the Vivado platform, the Tetris block written in the Verilog language can be downloaded on the FPGA hardware.)
User_IP
- 如何在 VIVADO 中创建用户自定义的IP(How to create user defined IP in VIVADO)
ug906-vivado-design-analysis
- ug906-vivado-design-analysis
Verilog秒表设计
- 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
Multi_cpu
- 多周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
cpu2
- 这是在vivado平台上编写的多功能流水线cpu的实现，是我们课程实验的大作业(This is the implementation of the multi-functional pipelined CPU written on the vivado platform. It's a big job for our course experiment.)
vivado常用综合属性
- vivado常用综合属性，可以帮助对设计进行约束(vivado commonly used attributes, can help to design constraints)
FPGA_VGA
- Vivado下采用Verilog语言实现VGA显示(Implementation of VGA display in Verilog language under Vivado)
dma_performance_demo
- 含全套PCIE调试文件：FPGA代码（Verilog），驱动文件及安装（包含Windows和Linux）(PCI_Express Vivado Windows Driver)
Lab 1
- FPGA XILINX VIVADO LAB
vc2015_x64_14.0.24215
- windows 7 安装VIVADO 需要(Microsoft Visual C++ 2015 Redistributable(x64) - 14.0.24215)
TFG_Comparativa_Deteccio_Cares
- 使用zynq去使用opencv，使用C++语言，编译器使用的vivado 2016，英文原版的，需要读者去自己翻译。(Use zynq to use opencv, use the C++ language, the compiler uses vivado 2016, the original English version, and requires readers to translate themselves.)
Vivado_2037
- vivado 2015.4 lisence
try
- 利用xilinx公司开发的vivado平台中的IP核-加法器，实现加法(The addition of IP core adder to the vivado platform developed by Xilinx is applied.)
test
- 利用xilinx公司开发的vivado平台中的IP核-rom，实现存储(Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.)
oo
- 利用xilinx公司开发的vivado平台，实现下变频功能(We use the vivado platform developed by Xilinx to realize the down conversion function.)
demo
- 利用xilinx公司开发的vivado平台，实现调用romIP核的功能(Using the vivado platform developed by Xilinx, the function of calling romIP core is implemented.)
one_1bit
- 利用xilinx公司开发的vivado平台，实现调用1bitpwm信号实现下变频的功能(Using the vivado platform developed by Xilinx, we can realize the function of calling down the 1bitpwm signal to realize the down conversion.)
xapp794
- 里面分为八个实验，一步一步教你使用system genertor for dsp 生成能供vivado使用的IP核文件。(It is divided into eight experiments, which teach you to use system genertor for DSP step by step to generate IP core files that can be used for vivado.)
initial_lib
- Vivado的初始库文件，内含74LS系列IP模块和XUP系列模块(The initial library file of Vivado contains 74LS series IP module and XUP series module.)