搜索资源列表
verilog
- vivado的led灯的学习程序，有兴趣学习soc的可以下载-the program for vivado study on SOC
EqualizeHist_hls
- 灰度图象直方图均衡化。使用vivado的HLS来实现直方图的均衡化。-Gray image histogram equalization. Use vivado of HLS to achieve histogram equalization.
sobel
- 基于FPGA的sobel滤波。使用vivado 2014.2实现的YUV图像的sobel滤波。-Sobel filter based on FPGA. YUV image Sobel filtering using vivado to achieve the 2014.2.
tb_axi4
- 介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.
sell-machine
- verilog sell machine 通过robei和vivado设计的建议xilinx测试程序，有助于学习vivado和fpga-verilog vivado xilinx
zybo_zynq_audio
- Zybo xc7z010 uation board,ssm6203音频编码器，PC端给音频输入，HPH输出口输出过滤噪音的音频，软件：xilinx vivado, vivado HLS, SDK-Zybo xc7z010 uation board, ssm6203 audio encoder, PC end to the audio input, HPH output port noise filter audio software:
Vivado_Zynq_Guide
- Vivado的简明教程及Zynq的开发流程-Vivado concise tutorials and Zynq development process
hdl-master
- ADI ad9361 vivado 下源代码-ADI ad9361 vivado source code
sin_wave
- 在vivado开发环境下，调用ram IP，实现可调频的正弦波信号发生器。-vivado IP signal generator
adder8
- 8位加法器源代码，vivado实现编写。-8 adder Source, vivado achieve write.
Vivado_debug_to_MATLAB_doc
- 介绍了Xilinx Vivado debug调试环境下，将调试数据导入MATLAB的方法，简单易用，欢迎交流-Guide for Xilinx Vivado debug, import data to matlab.
ug871_vivad_HLS_tutorial
- Xilinx Vivado HLS 高层次综合工具的软件使用说明-Vivado HLS Xilinx high level integrated tool for the use of software instructions
21ic_VIVADO-verilog
- vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA -vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA v
CLK_DIV_IP_packager
- Vivado IP packager的实例。Vivado版本2014.2，使用Verilog语言对一个分频程序打包。-Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.
DDR3_ip
- 本文档开发环境为vivado软件，描述了ddr3 IP core的生成过程，亲测可行。-this document describe ddr3 ip core genetator process.I test it by myself.
xadc
- 基于xinlinx的vivado的xadc设计代码-Based on the xinlinx vivado xadc design code
square_wave
- 利用Vivado的高层次综合实现了一个可调方波的HDL描述-use the Vivado to realize a square wave with adjustable period
delay_add
- 利用Vivado高层次综合实现的用HDL语言描述的时序的delay函数-realize a delay function, which is described by the Verilog, by Vivado
xilinx_license_2015
- Vivado Design Suite v2015.4版本license-the license of Vivado Design Suite v2015.4
7_VGA
- VGA屏幕上显示出白-红-绿-蓝的彩条信号。基于basys3，软件平台vivado-VGA screen display color signal of white- red green blue. Based on basys3 software platform, vivado