搜索资源列表
FSM
- 有限状态机,用Verilog语言,执行正确,仿真通过。-Finite state machine, with the Verilog language, the implementation of the right, simulation pass.
LIP1745CORE_uart_txfsm
- UART TX FSM Verilog source code
verilog
- verilog code for the decription of the fsm of the controller
FSMwithOutputsDecode
- 有限状态机FSM with Outputs Decoded in Parallel Output Register-FSM with Outputs Decoded in Parallel Output Register
FSMwithOutputsEncodedwithinStateBits
- FSM有限状态机FSM with Outputs Encoded within State Bits-FSM with Outputs Encoded within State Bits
USE_FSM_DEDIGN_SRAM
- 用FSM(有限状态机)设计SRAM的VHDL语言-With the FSM (finite state machine) design of the VHDL language SRAM
fsm
- VHDL新手入门:有限状态机练习(三段式结构)-VHDL Getting Started: Finite state machine exercises (three-stage structure)
FSM
- 用程序实现状态机功能,有限状态机是指输出取决于过去输入部分和当前输入部分的时序逻辑电路。一般来说,除了输入部分和输出部分外,有限状态机还含有一组具有“记忆”功能的寄存器,这些寄存器的功能是记忆有限状态机的内部状态,它们常被称为状态寄存器。在有限状态机中,状态寄存器的的下一个状态不仅与输入信号有关,而且还与该寄存器的当前状态有关,因此有限状态机又可以认为是组合逻辑和寄存器逻辑的一种组合。其中,寄存器逻辑的功能是存储有限状态机的内部状态;
statemachine
- RTL级verilog代码 用状态机实现 将输入数据写入16位寄存器,输出其除以7所得的余数(4位)-RTL-lever verilog code Using FSM to realize the following function:input the data into a 16bit register, divide it by 7, and output the 4-bit remainder
Example-6-1
- 1. Example-6-1\FSM\state1目录下为一段式FSM描述方法源码 2. Example-6-1\FSM\state2目录下为两段式FSM描述方法源码 3. Example-6-1\FSM\state3目录下为三段式FSM描述方法源码 4. Example-6-1\FSM\ state_default目录下为添加了default默认状态的源码 -1. Example-6-1 \ FSM \ state1
downsizer
- A FSM that extracts the 18 LSB out of a 128 bit vector and forwards it as a 18 bit vector.
FSM
- 文章介绍的状态机的优化写法,并给出经典实例。使读者更清楚的明了FPGA中状态机的优点,以便工程中的使用。-This paper introduces the optimization of state machines written, and gives the classic example. So that readers understand more clearly the advantages of FPGA in the
AD7938controllor-VHDL
- VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938-VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel
moore
- 摩尔有限状态机的例子很好的,实验读写控制-an example of FSM of moore
FSM
- 功能强大的汇编语言词法分析器,可以读入一行汇编语言,再输出扫描结果。使用汇编语言开发,有限自动机原理。-Powerful assembly language lexical analyzer, can be read into the line of assembly language, and then export the scan results. Assembly language development, finite aut
FSM-Based_Digital_Design_
- 对FPGA开发帮助很大,vhl中有限状态机设计精华-Great help for FPGA development, vhl essence of a finite state machine design
fsm_moore_3_always
- 使用3個always (三段式)來實現Moore FSM。 -Moore FSM
fsm_moore_1_always
- 使用1个always块描述Moore FSM(摩尔状态机)-Moore FSM 1 always
fsm-3_7.linux.i386.tar
- Toolkit to create finite-state machines on linux.
fsm-4_0.linux.i386.tar
- Toolkit for building finite-state machines on linux, version 4.