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FSM的示例程序
- 这是有限状态机的模版事例程序，很有意义。 请斑竹尽快给我下载权限。急。- Please fed as I downloaded to the authority. Urgent.
mealy FSM
- mealy fsm 和moore fsm-mealy Fsm and moore Fsm
uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
fsm_2006_12_26
- 关于FSM的使用，希望大家好好学习和推广这项技术-the use of the FSM, we hope to learn and to promote this technology
FSM_design_guide
- 在FPGA设计时常用到FSM设计,本文很好地指导如何设计FSM-in FPGA design often used FSM design, a good guide is how to design FSM
FSMGenerator10b7_reference
- FSM(有限状态机)代码生成器参考使用手册，windows环境-FSM (finite state machine) code generator reference manual, windows environment
FSMGenerator10b7_manual
- FSM（有限状态机）代码生成器设计指导，windows环境下使用 -FSM (finite state machine) code generator design guidance, windows environment
A_acm5
- 用C++实现人工智能控制，其内核为FSM，附件为实现工具 -With C++ Realize artificial intelligence control, and its core for the FSM, the annex for the realization of tools
FSM_Moore
- altera Quartus II FSM使用 可設定時間波形，手動調整波形頻率。 (含電路) -altera Quartus II FSM can be set using the time waveform, manually adjust the frequency waveform. (With circuit)
FSM_writing
- VHDL/Verilog FSM的优化写法-VHDL/Verilog FSM optimization formulation
fsm
- 检测输入数据中的“10110”序列，并记录检测到的序列的数目，当序列数目大于15时溢出。 输入信号：iclk //输入时钟 rst_ //复位信号 din //输入串行数据 输出信号：[3:0] catch //检测到的序列的数目 overflow //数目大于15 ，溢出 -Detection of input data of
ALTERA_DE2_FSM_VHDL
- This an exercise in using finite state machines.基于ALTERA的DE2开发 平台，设计一个有限状态机FSM(finite state machines).-This an exercise in using finite state machines. Based on ALTERA s DE2 development platform to design a finite stat
synopsis_FSM_coding
- synopsis的有限状态机编码方法的文档。 针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。 FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding
custom_focus_manager
- flash lite FSM 学习实例 FSM 按钮实例-flash lite FSM study examples of FSM examples button
microthreads
- Simple microthreads and fsm for microcontrollers using only preprocessor/inline code
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL codin
FSM
- 有限状态机状态转换，模拟实现状态转换使用hashtable-Finite state machine state transitions
yetert
- This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).