搜索资源列表
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
The-design-of-multiplier
- 国防科技大学的一篇高速乘法器算法的论文,应用于FPGA-National Defense University in a high-speed multiplier algorithm paper, used in FPGA
CCMU
- 代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less
multiplier
- 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
booth
- radix 2 booth multiplier verilog code
VHDL-Multiplier
- 资料是EDA的一个课程设计，基于VHDL实现的乘法器，包含论文，欢迎下载-EDA data is a course designed to achieve a multiplier based on VHDL, including paper, please download
multiplier
- 参数可配置的sequential 乘法器和booth 乘法器-verilog source code with configurable parameters for sequential multiplier and booth multiplier
array-multiplier
- source code for array multiplier
67719585-Booth-Multiplier-Vhdl-Code
- vhdl code for booth multiplier-vhdl code for booth multiplier...........................
multiplier-method
- 用乘子法求解约束优化问题。使用实例进行说明。程序给出。-With the multiplier method to solve the constrained optimization problem. Program are given.
multiplier
- 32位乘以32位乘法器，由datapath 和控制中心组成，输出64位结果-32bits by 32 bits multiplier
8-8-array-multiplier
- a multiplier structural code
Floating-Point-Multiplier-in-Verilog
- Floating Point Multiplier in Verilog
4-x-4-on-time-multiplier--table
- 4×4 查找表乘法器 vhdl 语言描述-4 x 4 on time-multiplier look-up table VHDL language describe
16-parallel-multiplier
- 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
wallace-tree-multiplier
- 关于fpga乘法器的一种算法，一种wallace树压缩器硬件结构的实现-An algorithm on fpga multiplier, a wallace tree compression hardware structure
multiplier
- 8*8的乘法器基于quartus2的显示文件，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，由于是第一次上传文件，这个是基于quartus2的显示文件-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
multiplier
- 8*8的乘法器，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
multiplier
- 8 bits multiplier module in verilog a[7:0]*b[7:0]=c[8:0] // only use one adder
HDL-of-multiplier
- 乘法器原理及HDL代码，里面文档包括几种乘法器的详细介绍和代码-Including several multiplier multiplier principle and HDL code, which document the details and code