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multiplier
- A VHDL program for multiplier, which has been used as a main source for a fir filter
verilog
- 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit*
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major d
multiplier
- 增广乘子法，优化算法程序，采用Fortran语言编写-Augmented multiplier method, optimization procedures, using Fortran language
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
4-multiplier-_vhdl
- 4 bit multiplier which can be use for making projects......can also be stimulated on spartan kits
Multiplier-method
- 乘子法求解约束方程 老师编的一段程序 注释非常详细-Multiplier method to solve a series of constraint equations teachers very detailed program notes
MULTIPLIER
- 基于VHDL硬件描述语言设计的乘法器，位数可以修改-VHDL hardware descr iption language based on the design of the multiplier, the median can be modified
multiplier_ip
- 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
Multiplier
- VHDL语言设计的乘法器，经过试验箱测试通过，用试验箱的8个拨码开关输入数字，按键按下输出结果。-VHDL language design of multiplier, after chamber test, with the chamber of the 8 DIP switch input numbers, key press output.
lagrange-multiplier
- Larange Multipliers-Larange Multipliers...........
VHDL-based-8-bit-multiplier
- 基于VHDL的8位乘法器运算程序，运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
carry-save-multiplier-Verilog-code
- 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
lowpower-multiplier
- 32位无符号低功耗的乘法器,经过10000次测试,用smic.13工艺,DC综合后,延时为8ns,功耗仅为635uw.-it is an unsigned 32bit multiplier.100000 benchmarks have been tested and all of them passed. With smic 0.13um process library, after disign complier analysis,
8bit-Shift-and-Adder--multiplier
- 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
4-bit-multiplier
- 4 bit multiplier program using shift and multiply
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, w
Small-multiplier
- 小型倍频器，简单的介绍了如何用verilog写倍频电路》-Small multiplier
VHDL-test-codeBooth-multiplier
- VHDL实验代码：Booth乘法器，是一个基于VHDL语言开发的程序，非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical