搜索资源列表
MIPS
- mips处理器指令仿真器，可查看流水线执行方式-mips instruction processor emulator, you can review the pipeline implementation
pipeline
- 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧-About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Pipeline_FFT
- Descr iption of a pipeline architecture for a FFT processor, based on the R22SDF algorithm.
Pipeline
- java写的关于流水线工作过程的模拟程序-java to write the work on the assembly line process simulation program
float_data_multiple_use_fixed_pipeline_verilog_pro
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！-a program of float multiply, using 3-stage pipeline technology
add
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
GPUGems1
- GPU Gems is a compilation of articles covering practical real-time graphics techniques arising from the research and practice of cutting-edge developers. It focuses on the programmable graphics pipeline available in toda
MIPS
- 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Pipeline
- 计算各油井到主管道之间的输油管道最小长度总和。-Pipeline
waterline_adder
- 这是一个用Verilog编写的四级流水线加法器-This is a Verilog prepared with four pipeline adder
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
pipe
- This an example of pipeline implemented in SystemC-This is an example of pipeline implemented in SystemC
Fire
- firestarter – A Real-Time Fire Simulator Many obstacles exist in attempting to graphically render physical phenomena that are highly fluid and ostensibly chaotic in nature. Fire is a prime example of such phenomena
cordic
- vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
pipe3
- 模拟Y86系统，可以让学习pipeline的学生更清楚明白的了解这个系统的内涵-Y86 simulator
fir_512_378_mux
- 512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
16bit_pipeline
- 16 bit pipeline design by vhdl.
ADCtestprogram
- adc 的测试程序,测试adc的各种静态和动态特性。-the testing program of pipeline adc
arm7
- ARM7 VERILOG源码，非常精简，3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline