搜索资源列表
dpll
- 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
dpll_demo
- 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successfu
DPLL_Circuit
- 本文在说明全数字锁相环的基础上，提出了一种利用FPGA设计一阶全数字锁相环的方法，并 给出了关键部件的RTL可综合代码，并结合本设计的一些仿真波形详细描述了数字锁相环的工作过程，最后对一些有关的问题进行了讨论。-In this paper, that all-digital phase-locked loop based on a FPGA design using first-order DPLL method, and give
clkrecoveryDPLL
- 用于时钟恢复的全数字锁相环设计，可以去掉时钟的抖动。-Clock recovery for all-digital phase-locked loop design, the clock jitter can be removed.
DPLL_verilog
- 一阶全数字锁相环VERLOGIC程序代码，调试通过。-First-order DPLL VERLOGIC program code, debugging through.
Matlab_model
- 在MATLAB环境下，对全数字锁相环的仿真，分析锁相环的性能参数-In the MATLAB environment, to all-digital phase-locked loop simulation, analysis of the performance parameters of phase-locked loop
3DPLL_fangan
- 介绍了数字锁相环的3种设计方法，并对各自的工作原理做了详细分析。-Introduction of digital phase-locked loop of three kinds of design methods, and their working principle to do a detailed analysis.
weifenqi
- 微分器：利用数字锁相环进行位同步信号提取的关键模块-Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules
dpll_fpga
- 基于FPGA设计数字锁相环，提出了一种由微分超前/滞后型检相器构成数字锁相环的Verilog-HDL建模方案-FPGA-based design of digital phase-locked loop, a by the differential ahead of/lag type seizure constitutes a digital phase-locked loop phase of the Verilog-HDL mode
adpll
- 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
pll
- 数字锁相环教案。 数字锁相环教案。-DPLL lesson plans. DPLL lesson plans.
sxh
- 一个初步的数字锁相环程序，没有测试文件，应该可以运行。-DPLL an initial procedure, there is no test file should be able to run.
MCU020
- 数字锁相环控制产生信号程序详解以及控制字计算方法-DPLL Detailed procedures for the control signal and the control method of calculating the word
PLL
- 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！-Abroad, a good digital phase-locked loop (PLL) design documents (after extracting PLL.pdf), can not look at Yo!
pll1
- 该程序实现的功能是数字锁相环的设计。源代码可以直接进行仿真试验◎-The program s function is to achieve the design of digital phase-locked loop. Source code can be directly carried out simulation test ◎
DigitalPLL
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。
pll
- 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
myDPll
- 本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
FPGA-DPLL
- 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.