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matlab simulink 锁相环程序
- 这是一个用simulink仿真锁相环的程序，介绍了模拟锁相环与数字锁相环的仿真原理
02
- 基于VHDL的全数字锁相环的设计 有关键部分的源代码 hehe !-VHDL-based all-digital phase-locked loop has a key part of the design of the source code hehe!
gfuzzy
- 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.-Based on fuzzy logic control of digital phase-locked loop for the communication
MC145152
- 1、数字锁相环的单片机代码。 2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.
dxz
- 低相噪、低杂波数字锁相环路滤波器的设计,caj格式，下载前请安装相应阅读器-Low phase noise, low-noise digital phase-locked loop filter design, caj format, download the pre-install the corresponding reader
006
- 基于FPGA实现的一种新型数字锁相环-Based on the FPGA realization of a new digital PLL
newDPLLdesign
- 使用VHDL语言进行数字锁相环的设计，pdf格式，可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields ha
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
PLL_grt_rtw
- C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demo
FPGA-based-design-of-DPLL
- 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. H
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divi