搜索资源列表
Tun2CNk2
- FPGA实现DSP的Verilog 示例-FPGA realization of DSP-Verilog Example
DM9000A_IPcose
- 如题：dm9000aＩＰ核，经过验证，可用-Such as the title: dm9000aIP nuclear, after verification, can be used
sine
- Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
spi_master
- 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Y312448
- 基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！-VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!
05805
- 无线通信fpga设计matlab、verilog代码
adpll
- 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
combine_module
- 本代码根据包头、包尾指示，将两路数据合路调度成一路输出-The code according to Baotou, including the end of the instructions will be two-way data path scheduling together all the way into the output
sinfunction
- 用cordic算法实现超越函数,sin,cos用此方法也可以实现其他的sinhx,coshx,ex.代码用verilog编写-CORDIC algorithm with transcendental function, sin, cos by this method can also realize other sinhx, coshx, ex. Verilog code used to prepare
PLL
- PLL 时钟模块 Quartus II平台的简单设计实例 附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
dac0832_VHDL
- 用Verilog HDL编写的0832源程序，实现对0832实现D/A转换。也可方便地转换为vhdl源程序。-Prepared by using Verilog HDL source code 0832, 0832 to achieve the realization of D/A conversion. Also can be easily converted to VHDL source code.
usb_funct
- usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
I2C_verilog
- 用verilog设计了一个简洁而实用的I2C总线控制器，对大家学习FPGA和I2C总线接口等相关方面的知识有较大的帮助。-Verilog design using a simple and practical I2C bus controller, for everyone to learn FPGA and I2C bus interface and other related knowledge has a greater help
rs422
- rs422接 VHDL语言编写 chipescope仿真通过-RS422 access chipescope language VHDL simulation through
7670_YUV_VGA_20fps_rev_1.1
- ov7670 VGA寄存器配置,由ov公司提供-Register ov7670 VGA configuration, provided by the ov
rake_mrc
- 实现RAKE接收机的最大比合并准则，输入位宽16比特。-RAKE receiver to achieve the maximal ratio combining criteria, enter the 16-bit wide.
cordic
- verilog源代码，用于软件无线电中，cordic函数-Verilog source code for software radio, cordic function
f2
- 96位矩阵循环乘法，verilog实现，-96 matrix multiplication cycle, verilog realized,
fqdivider
- 数字积分dda直线插补器 希望与数控系统设计的朋友一起学习进步-The number of points straight dda Interpolator hope and numerical control system designed to study the progress of friends