资源列表
[VHDL编程] div_fru
说明:介绍分频器的好资料。不光有奇数分频、偶数分频,还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。-Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not<chengpan> 在 2025-07-05 上传 | 大小:14kb | 下载:0
[VHDL编程] frenquent
说明:分频器的一些程序。包括整数分频,小数分频,我感觉非常好的资料,不敢私自分享。特拿出来分享。希望想学习的好好参考下,肯定会有所感悟。-Divider of some procedures. Including the integer frequency, fractional, and I feel very good information, not privately share. Point out to share. They want to study more carefully th<chenkuijiao> 在 2025-07-05 上传 | 大小:15kb | 下载:0
[VHDL编程] DDS_100325(13)_success
说明:QUARTUS II环境下VHDL语言编写DDS程序,双数字信号输出,一为正弦波幅值输出,一正弦波差值信号。时钟2^21HZ,带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bi<骆东君> 在 2025-07-05 上传 | 大小:1.04mb | 下载:0
[VHDL编程] 190.7_Freq_divider
说明:QUARTUS II环境下VHDL编写的小数点分频器程序,实现190.7分频,可以将50MHz时钟频率分频成约等于2^21Hz频率,方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas<骆东君> 在 2025-07-05 上传 | 大小:320kb | 下载:0
[VHDL编程] iiscode
说明:用Verilog写的一个简单的IIs控制器,分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。 另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and syn<hgdai> 在 2025-07-05 上传 | 大小:591kb | 下载:0