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[VHDL编程gray

说明:基于Verilog的GRAY计数器。以及测试文件,在simulation的文件件中的top文件。-Based on Verilog, GRAY counter. And test files, the files in the simulation of the top pieces of the file.
<栾帅> 在 2025-06-18 上传 | 大小:2.31mb | 下载:0

[VHDL编程38018066-VHDL

说明:INTRODUCTION § The VHSIC Hardware Descr iption Language (VHDL) is an industry standard language used to describe hardware from the abstract to concrete level. § The language not only defines the syntax but also defines very clear simulation
<phitoan> 在 2025-06-18 上传 | 大小:125kb | 下载:0

[VHDL编程50973937-VHDL-Report

说明:Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For s
<phitoan> 在 2025-06-18 上传 | 大小:993kb | 下载:0

[VHDL编程34105908-Multipliers-Using-Vhdl

说明:ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
<phitoan> 在 2025-06-18 上传 | 大小:371kb | 下载:0

[VHDL编程38504873-pll

说明:Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
<phitoan> 在 2025-06-18 上传 | 大小:358kb | 下载:0

[VHDL编程40716003-VHDL

说明:What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
<phitoan> 在 2025-06-18 上传 | 大小:86kb | 下载:0

[VHDL编程44317447-Vhdl-Sim-Syn

说明:This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente
<phitoan> 在 2025-06-18 上传 | 大小:107kb | 下载:0

[VHDL编程hidoh

说明:汇编计数器,可以在计算机上直接运行的软件程序-Compilation of the counter, you can run directly on a computer software program
<shjt> 在 2025-06-18 上传 | 大小:6kb | 下载:0

[VHDL编程rk

说明:this code is Universal Asynchronous Transreciver this project is IEEE 2008 standard this project is done by my personal and i had verilog code.
<chandu> 在 2025-06-18 上传 | 大小:5.67mb | 下载:0

[VHDL编程HDB3_encoder_QuartusPrj

说明:
<张昕> 在 2025-06-18 上传 | 大小:12.58mb | 下载:0

[VHDL编程open_cores_VGAcore

说明:老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
<张昕> 在 2025-06-18 上传 | 大小:2.05mb | 下载:0

[VHDL编程MIT[1].Press_.Circuit.Design.with.VHDL._2004_.TLF

说明:This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
<Psycho> 在 2025-06-18 上传 | 大小:4.82mb | 下载:0
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