[VHDL编程] 38504873-pll

说明：Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
<phitoan> 在 2026-01-02 上传 | 大小：358kb | 下载：0

[VHDL编程] 40716003-VHDL

说明：What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
<phitoan> 在 2026-01-02 上传 | 大小：86kb | 下载：0

[VHDL编程] 44317447-Vhdl-Sim-Syn

说明：This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente
<phitoan> 在 2026-01-02 上传 | 大小：107kb | 下载：0

[VHDL编程] hidoh

说明：汇编计数器，可以在计算机上直接运行的软件程序-Compilation of the counter, you can run directly on a computer software program
<shjt> 在 2026-01-02 上传 | 大小：6kb | 下载：0

[VHDL编程] rk

说明：this code is Universal Asynchronous Transreciver this project is IEEE 2008 standard this project is done by my personal and i had verilog code.
<chandu> 在 2026-01-02 上传 | 大小：5.67mb | 下载：0

[VHDL编程] HDB3_encoder_QuartusPrj

说明：
<张昕> 在 2026-01-02 上传 | 大小：12.58mb | 下载：0

[VHDL编程] open_cores_VGAcore

说明：老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
<张昕> 在 2026-01-02 上传 | 大小：2.05mb | 下载：0

[VHDL编程] MIT[1].Press_.Circuit.Design.with.VHDL._2004_.TLF

说明：This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
<Psycho> 在 2026-01-02 上传 | 大小：4.82mb | 下载：0

[VHDL编程] server

说明：This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
<Psycho> 在 2026-01-02 上传 | 大小：1kb | 下载：0

[VHDL编程] vending

说明：This is verilog vending machine code. We can eat beverage and soda with only $1.25 This decribes all schematic and state diagram. Ducksooyo~
<Psycho> 在 2026-01-02 上传 | 大小：110kb | 下载：0

[VHDL编程] Design-AND-gate

说明：通过应用QUARTUSII开发软件对与门的设计（二输入）和D触发器的设计。 -QUARTUSII development through the application of software and door design (two inputs) and the D flip-flop design.
<renee> 在 2026-01-02 上传 | 大小：2kb | 下载：0

[VHDL编程] Multiplexer-Description

说明： 通过应用QUARTUSII开发软件对二选一多路选择器进行设计并运行结果-Software development through the application of QUARTUSII choose one of two multiplexer design and operation results
<renee> 在 2026-01-02 上传 | 大小：10kb | 下载：0