[VHDL编程] aescore

说明：基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
<李华> 在 2025-06-09 上传 | 大小：191kb | 下载：0

[VHDL编程] tut_simulation_verilog

说明：This tutorial introduces the basic features of the QuartusII Simulator.
<Nguyen Chi Nhan> 在 2025-06-09 上传 | 大小：294kb | 下载：0

[VHDL编程] SequentialCircuitDesign_withVerilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-06-09 上传 | 大小：292kb | 下载：0

[VHDL编程] tut_quartus_intro_verilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-06-09 上传 | 大小：800kb | 下载：0

[VHDL编程] tut_timing_verilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-06-09 上传 | 大小：361kb | 下载：0

[VHDL编程] Verilog_VHDL_Golden_Reference_Guide

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-06-09 上传 | 大小：272kb | 下载：0

[VHDL编程] Crack_Altera_Quartus61.0-9.1

说明：Crack_Altera_Quartus61.0-9.1.rar license-Crack_Altera_Quartus61.0-9.1.rar license!!!
<guobo> 在 2025-06-09 上传 | 大小：257kb | 下载：0

[VHDL编程] 80C51_1

说明：1.异步通信软件模拟2.基于RS-232的串口通信3.基于RS-485的多机通信4. I2C总线协议的软件实现5. SPI总线在单片机系统中的实现6.-wire-1. Asynchronous communication software simulation 2. Based on the RS-232 serial communication 3. Based on the RS-485 Multi-machine communication 4. I2C bus protocol soft
<hdm> 在 2025-06-09 上传 | 大小：63kb | 下载：0

[VHDL编程] keyscan

说明：2×8 键盘扫描编程--- VHDL语言-2×8 keyboard scan---VHDL language
<rjy> 在 2025-06-09 上传 | 大小：1kb | 下载：0

[VHDL编程] simple_pic

说明：一个通用中断系统的Verilog HDL描述，对想了解知道是怎么实现的读者，可以查看综合出来的电路，会有很大帮助！-A common interrupt system of the Verilog HDL descr iption of the would like to know how to achieve the readers know, there will be of great help!
<陈永恒> 在 2025-06-09 上传 | 大小：436kb | 下载：0

[VHDL编程] irq_decoder

说明：中断优先编码器的描述，输出中断向量供CPU读取，非常好用，只要稍稍修改，就可以产生您所需要的中断向量。-Descr iption of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need.
<陈永恒> 在 2025-06-09 上传 | 大小：219kb | 下载：0

[VHDL编程] FIR

说明：FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
<蓝晶> 在 2025-06-09 上传 | 大小：5kb | 下载：0