资源列表
[VHDL编程] FPGA-design-and-debug-
说明:FPGA的设计与调试(专家技术演讲稿免费下载)-FPGA design and debug (expert technical presentations for free download)<jizhendong> 在 2025-06-09 上传 | 大小:2.97mb | 下载:0
[VHDL编程] Controllable-digital-clock
说明:可控数字钟,通过串口实现红外发射接收,旋转LED实现时间同步显示-Controllable digital clock, through the serial port infrared transmitting and receiving rotating LED time synchronization display<mike> 在 2025-06-09 上传 | 大小:31.43mb | 下载:0
[VHDL编程] project1_supplemental1
说明:these are projects based on verilog like memory control, sdram control etc-these are projects based on verilog like memory control, sdram control etc..<neeraj> 在 2025-06-09 上传 | 大小:1.68mb | 下载:0
[VHDL编程] CPLD240_138trans
说明:CPLD240_三八译码器 CPLD 源代码-CPLD240 3-8<liyiyu> 在 2025-06-09 上传 | 大小:164kb | 下载:0
[VHDL编程] mini_cpu_verilog
说明:用verilog写的简单的CPU,有详细注释-Use verilog to write a simple CPU, with detailed notes<> 在 2025-06-09 上传 | 大小:145kb | 下载:0
[VHDL编程] FIFO
说明:先入先出队列(First Input First Output,FIFO)这是一种传统的按序执行方法,先进入的指令先完成并引退,跟着才执行第二条指令。-FIFO queue (First Input First Output, FIFO) which is a traditional sequential execution method, first enter the command to finish and retire, only to follow the implementatio<吴海勇> 在 2025-06-09 上传 | 大小:1kb | 下载:0
[VHDL编程] frequency5x2
说明:frequency5x2实现频率的分频,5*2即实现10分频,主要用于满足有些控制类的频率时钟。-frequency5x2 realize the frequency divider, 5* 2 frequency of achieving 10 points, mainly used to control the class to meet some of the frequency of the clock.<吴海勇> 在 2025-06-09 上传 | 大小:3kb | 下载:0
[VHDL编程] sequence_dectect
说明:sequence_dect 实现6个状态,即6种选择的状态机。状态机的一个极度确切的描述是它是一个有向图形,由一组节点和一组相应的转移函数组成。-sequence_dectect to six states, namely, six options the state machine. State machine of an extremely precise descr iption is that it is a directed graph, by a group of nodes and<吴海勇> 在 2025-06-09 上传 | 大小:1kb | 下载:0