资源列表
[VHDL编程] mdio-md
说明:目前以太网PHY芯片是通过总线MDC/MDIO,但是基本上是通过MAC芯片直接管理的,本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理-At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA<leon> 在 2025-06-14 上传 | 大小:2kb | 下载:1
[VHDL编程] MedFilter_VHDL
说明:用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法,而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.<mike.chen> 在 2025-06-14 上传 | 大小:2kb | 下载:0
[VHDL编程] dffasynchronous
说明:this ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element-this is ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element<sri> 在 2025-06-14 上传 | 大小:2kb | 下载:0
[VHDL编程] 115157718cmos_FPGA
说明:一本关于FPGA详细介绍的图书,很详细,很精彩,经典-FPGA a detailed introduction about the book, very detailed, very exciting, classic<zhangyan> 在 2025-06-14 上传 | 大小:2kb | 下载:0
[VHDL编程] FPGA-SRAMt-test
说明:测试型号为EP2C5Q208C8的FPGA的RAM是否正常,按提示操作,并显示每步的测试结果-EP2C5Q208C8 test models for the FPGA' s RAM and whether it is normal, according to prompts, and display each step of the test results<冀少威> 在 2025-06-14 上传 | 大小:2kb | 下载:0
[VHDL编程] chufaqi
说明:时序电路是指它的输出不仅取决于当时的输入,而且也取决于过去的输入,即过去输入不同,则在当前的情况下,输出也可能不同。-Sequential circuit is the output depends not only on its input at that time, but also on past input, that is different from the last input, then in the current circumstances, the output also<hellen> 在 2025-06-14 上传 | 大小:2kb | 下载:0