[VHDL编程] Chapter-1

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
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[VHDL编程] Chapter-2

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
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[VHDL编程] Chapter-3

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
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[VHDL编程] Chapter-4

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
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[VHDL编程] Chapter-5

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
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[VHDL编程] 2DPSK

说明：vhdl,Digital phase modulation is also known as phase shift keying, 2DPSK is binary differential phase shift keying, is a kind of digital phase modulation. Digital phase modulation using carrier phase change to transmit digital signal, usually can be
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[VHDL编程] Chapter-6

说明：练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
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[VHDL编程] Chapter-7

说明：练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
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[VHDL编程] Chapter-8

说明：练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
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[VHDL编程] DE2-user-Manual-(Chinese-edition)

说明：DE2板教学开发板中文用户手册,DE2板的着眼于为在数字逻辑，计算机组织和FPGA 方面的学习提供一个理想的工具。-DE2 user Manual (Chinese edition)
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[VHDL编程] uart_verilog

说明：用verilog语言编写的UART通信，经过调试可用。-edited in verilog language
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[VHDL编程] div3

说明：实现三分频功能，占空比为50 ，可以很好的用于解决课程设计问题！-This is used for divide the frequency,and the duty cycle is 50 .
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