搜索资源列表
countqi
- 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
xapp290
- 从Xilinx网站上下的，学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.
RS_decoder
- rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
eathnet
- 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
I2CSlave
- Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
lru_new
- 采用LRU替换算法。这种算法选择最久没有被访问的块作为被替换的块。 为了实现LRU算法，要在块表中为每一块设置一个计数器（cnt0，cnt1，cnt2，cnt3，）。计数器的长度为2位。-using LRU replacement algorithm. This algorithm to choose the most long visit is not being replaced as a block by block. To
m16550a_verilog_rtl
- mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
FSM_Westor
- 状态机得用法，可以帮助新手了解状态机得用法以及掌握用途-state machine in use, and can help newcomers understand the state machine in use, and control purposes
lcd12
- 基于ＡＬＴＥＲＡ公司的ＤＥ２的ＬＣＤ显示程序，一起学习．非常好的资料，也非常难得．是我参加培训时所得-the DE2 LCD display program, learning together. Very good information, and they are extremely rare. I receive training
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
randn
- 随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!-random sequence generator, m is a sequence, generating function will be included in the inside, for four bit-can be changed!
permute
- 交织器的一部分,可以生成交织索引函数,如果加上一个随即序列发生器就可以组成一个交织器 了!-interleaver part of the index can be generated intertwined function, If coupled with a sequence generator immediately on the formation of a interleaver!
multiplex
- 复接程序,用quartus运行的,可以把很多个信号复接在一起,是程序的一部分!-Multiplexing procedures used quartus operations, can put a lot of signal multiplexing together, is part of that process.
demultiplex
- 是用verilog写的,解复接程序,可以把复接的反过来,一般用在解码程序中!-verilog is written, Demultiplexer procedures can multiplexing the contrary, generally used in the decoding process.
performance
- 用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!-verilog prepared using the procedures used to calculate the error rate. the encoding and decoding process used in the!
pc104_fpga
- pc104接口的verilog代码，仅供参考-pc104 verilog interface code for reference purposes only
mt48lc2m32b2
- the verilog model of sdram-mt48lc2m32b2 device.-the verilog model of sdram - mt48lc2m32b2 d evice.
Plant
- 这些代码是用L-system语言，L-studio编译环境来实现相关功能的。主要是在实验室中的科研需要而编写的。 -these codes is L-system language, L-studio environment to compile the relevant functions. Mainly in laboratory research needs prepared.
dso_keyboard
- 本文件用于spi接口的键盘扫描模块，采用Verilog语言.-spi this document for the keyboard interface scanning module, using Verilog language.
uartvhdl
- 一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART