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mp3if
- 通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接，可以用于MCU需要与提供I2C接口器件通信的场合。-through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C I
des-verilog
- des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
数字锁相环dll_code
- 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
second&clk
- 开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路
m序列
- Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
jtag_verilog
- verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU
PCI总线仲裁参考设计，Quicklogic提供
- PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
8051IPcore，verilogHDL实现
- 用verilog写的很好的cpu core-using Verilog write a good cpu core
CPLD的跑馬燈
- cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
niosII_cyclone_1c20
- nios 的开发程序，主要是针对LCD 的多口设计金额初始化-the development process is targeted mainly LCD design of the Multi-rate Initialization
sorce
- 一个很好的利用verilog编程实现的cpu程序，一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.
hjs Verilog
- 是verilog例子。初级适用。包括了简单的例子。-example. The initial application. Including a simple example.
VerilogHDL
- Verilog HDL程序，对硬件开发有兴趣或需要的朋友赶快down下来-Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down
bcd_to_binary
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bcd码转bin-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, code switch bin bcd
binary_to_bcd
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bin转bcd-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, bin turn bcd
reg_8_io_clrset
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，reg的io口软件-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, the io I reg software
auto_baud_with_tracking
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，自动band跟踪小程序-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors, automatic tracking small band procedure
CPUverilog
- pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.