搜索资源列表
UART_BooQuai
- FPGA上实现UART串口原程序，在ISE6编写的-FPGA serial UART to achieve the original procedure, the preparation of the ISE6
collectionOfImageAndinterpolation
- 该系统是一个实现图像数据采集以及对图像数据的插值处理，供其它系统进一步处理或显示的系统。具有一定的通用性，适合大多数CMOS图像传感器接入。1准确、适时的数据采集，尽量减少延迟 2采集模块具备一定的数据缓冲功能 3快速有效的数据插值 4使用较少的逻辑器件和存储器 5代码的可读性要强 -The system is a realization of image data acquisition and the image data in
FIR_1
- FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
xapp195
- signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
sdramcore
- sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors
sram_verilog
- 告诉图形采集 verilog代码 很简单的 第一次发-tell graphics Acquisition Verilog code is very simple first grant
color_space_converter
- verlog 编程 色彩空间转换 有测试文档-verlog programming color space conversion is testing documents
ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
entropy_coding
- 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His descr iption of coding (entropy coding) for image compression test files are encoded
run_length_coding
- 用verilog 编写 应用于图像压缩编码中 使用行程长度编码(run lengthencoding,RLE)对交流系数(Aa)进行编码。-using Verilog prepared for image compression coding using length encoding (run leng thencoding, RLE) on the exchange coefficient (Aa) coding.
verilog_jpeg
- 用verilog 描写 应用于数字图像压缩系统--jpeg 有测试文档-using Verilog descr iption applied to digital image compression system -- a test jpeg files
PCIarbitration
- 这是PCI 仲裁机制的VHDL源码，它实现了PCI仲裁机制。-PCI arbitration mechanism VHDL source code, it achieved a PCI arbitration mechanism.
desimplementation
- 一个关于DES算法的verilog语言实现,包括了各个实现模块以及测试模块-a DES algorithm on the Verilog language, including the realization of the various modules and test modules
VLSIrtl_spi
- verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.-Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
7led
- 7段发光二极管vhdl程序，可以验证led的fpga验证程序-seven of the light-emitting diode VHDL procedures can verify they simply led to the certification process
buzz
- 一个用vhdl语言编成的可以让蜂鸣器发声的的程序。-with a monument of the VHDL language allows the buzzer of the procedure.
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
pwmvhdl
- 一个在xilinx的ise环境下编译仿真成功的pWM程序。-one of the Xilinx environment ideally compiler pWM success of the simulation procedures.
keybyise
- 一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。-a company embarks on the environment and ideally compile successful simulation keyboard operations.