搜索资源列表
fifo1616
- FIFO先入先出堆栈，包括三个子程序，可根据需要选择-FIFO first in-first stack, including three subprogram, according to choose
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse freq
avalon_slave_pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
reg_file
- NIOS环境PWM的USER LOGIC实例3-NIOS environment PWM USER Logic Example 3
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
lcd_controller
- CFAH1602BNYAJP液晶的fpga控制程序-CFAH1602BNYAJP they simply control procedures
uart_verilog_v1
- uart d的verilog 程序，可以实现普通串口功能-UART d Verilog procedures can be achieved ordinary serial port function
C_16450_edit
- 16450异步通讯接口，ALDEC提供，修正版（由网友zhy修改，修正一些错误-16450 asynchronous communications interface, providing ALDEC, the revised version (from netizens. Changes amendments to some errors
crc_verilog_xilinx
- CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
Verilog_traffic
- Verilog 的交通灯的例子。源代码中有详细的注释。-Verilog traffic lights examples. The source code for detailed comments.
RD1006
- VHDL编程 : out std_logic -- Transmitter control DataBits : in std_logic_vector(1 downto 0) StopBits : in std_logic_vector(1 downto 0) ParityEnable: in std_logic ParityEven : in std_logic ParitySti
control0
- systemverilog编写的cpu读写mem程序-SystemVerilog prepared by the cpu readers mem procedures
fifo0
- systemverilog编写的fifo例子-SystemVerilog examples prepared by the fifo
alu_inverter
- 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
sale2
- sale，自动收获机。首先投币，然后买东西，然后退币-sale, automatic harvester. The first coin, and then buy something, and then coin
ADD_SUB
- 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
uart2
- uart 通用异步接受机 编译环境为quartus-UART Universal Asynchronous Receiver and build environment for Quartus
Traffic_Light_Final
- Traffic light written with Verilog-written with Verilog
final_code
- mining source code written in Verilog
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified