搜索资源列表
alu_vlog
- 学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
VerilogHDL
- Verilog HDL程序，对硬件开发有兴趣或需要的朋友赶快down下来-Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down
RISC8.ZIP
- 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse freq
用cpld实现曼彻斯特编码
- 用cpld实现曼彻斯特编码 用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
HDLDumpCmd
- PS2游戏硬盘直灌（HDL）的Windows下VC的源代码，根据HDUMP修改的（改正了几处错误）。命令行方式执行，具体使用说明可在命令行中看到。HDP.exe是执行程序。-PS2 drive straight Irrigation (HDL) VC Windows source code According HDUMP amended (corrected several errors). Command-line approach
crc_16
- 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
veriloghdl快速入门
- verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware descr iption language procedures
ARM_Core
- arm verilog hdl ip core-arm Verilog HDL core ip
qep_data_bus
- 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的-address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL
verilog_UART
- UART verilog hdl 实现-UART Verilog HDL achieve
taxi1
- 出租车计价器，简单、方便，采用verilog hdl语言编写，所用平台是MAXPLUS软件-Taximeter, simple, convenient, using Verilog HDL language, by using the platform of software Segments
scu_all_fpga
- 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
keyboard_ps2_verilog
- 键盘鼠标的原代码,用FPGA实现,使用Verilog HDL编写,已经使用FPGA验正过了,完全可以用-keyboard and mouse of the original code, using FPGA, using Verilog HDL preparation, already in use FPGA-mortem is over, it can be used
Verilog_HDL_Hardware_Description_Language
- 正式出版物《Verilog HDL 硬件描述语言》一书的精美 PDF 电子版。-official publications "Verilog HDL Hardware Descr iption Language," a book of exquisite electronic PDF version.
hdl_coding_style
- HDL编程风格，很有用,希望对大家有所帮助。-HDL programming style, very useful, we want to help.
verilog_vga
- 用verilog HDL 语言写的在显示器上显示图案的源程序-with Verilog HDL language written on display in the pattern of the source
verilog_lcd
- 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
uartvhrilog
- This Verilog HDL descr iption implements a UART.