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Design_and_Test_VerilogHDL
- Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples a
div2
- 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit dec
VerilogHDL_clock
- 基于Verilog HDL设计的多功能数字钟，有兴趣的-Verilog HDL-based design of multi-function digital clock, interested
uart2iic
- UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-UART to I2C of the Verilog HDL code, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher prepar
demo_24c01a
- 24C01A的Verilog HDL仿真代码，用于I2C接口模块的测试，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-24C01A simulation of Verilog HDL code for the I2C interface module of the test, by the Beijing University of Posts and Telecommunications VerilogHDL
digtalclk
- 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realizatio
VerilogHDLdigitaldesigncode
- Vlerilog HDL高级数字设计源码，有兴趣者可以来看看，保证是完整版-Advanced Digital Design Vlerilog HDL source, who are interested can look at it, guaranteed to be the full version
AD7865test1
- verilog hdl写的利用fpga控制ad7865进行多路ad数据采集的程序源代码。-err
VerilogHDL
- 《设计与验证Verilog HDL》光盘内容-err
VerilogHDL_counter
- 采用Verilog HDL语言编写的数字频率计，被测波形分别为方波、三角波和正弦波；采用6个数码管显示结果，三档量程可调，工程价值很高，-err
VerilogHDL_trafficlight
- 采用Verilog HDL语言编写的交通灯控制系统，这是一个完整的毕设课题，分别有分频、显示译码、倒计时和动态显示驱动模块，实用价值很高，-Using Verilog HDL language of the traffic lights control system, which is a complete set of BI subjects who were frequent, indicating decoding, countd
altera_tft_lcd_controller
- Altera 开发环境下的VGA控制源码，Verilog HDL语言编写，支持sopc环境下操作以及驱动-Altera development environment under the control of VGA source, Verilog HDL language to support the SOPC operating conditions, as well as drive
simple_MCU
- 设计CPU方法及流程！VERILOG hdl-CPU design methods and processes! VERILOG hdl
verilog
- 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容-Department of Microelectronics, Peking University in the teacher s courseware mts on Verilog HDL, Cadence Verilog simulator c
VerilogHDL
- VerilogHDL硬件描述语言(简单的Verilog HDL语法-VerilogHDL Hardware Descr iption Language (Verilog HDL simple grammar
dul_ram(yk)
- 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
cordic
- cordic算法的Verilog HDL具体实现-CORDIC algorithm specific realize Verilog HDL
LCD_Driver
- LCD的驱动程序 用verilog HDL 编写 可以用于FPGA上 经过测试 可以使用-LCD driver with verilog HDL can be used for the preparation of the FPGA can be tested using
SourceFile
- PS2鼠标实验Verilog HDL代码-PS2 mouse experiments Verilog HDL code
Fusion_UART
- UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA