搜索资源列表
Verilog_HDL_language_learning
- Verilog HDL语言练习与讲解 里面有很多实用的源代码-Verilog HDL language exercises on the inside and have a lot of useful source code
VerilogHDL
- Verilog HDL 华为入门教程-网络上比较经典的学习资料-Verilog HDL Tutorial Huawei- Network Learn more classical information
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
VerilogHDL_code
- 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix k
SPI_verilog_mycode
- 基于Verilog HDL的SPI代码，可在FPGA上实现SPI接口，请大家参考-Verilog HDL based on the SPI code, implementation in FPGA on SPI interface, please refer to
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and m
Microprocessor
- 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
HuaweiFPGAdesignflowguide
- 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
traffic
- verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言-verilog HDl traffic light
fpadd
- 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Verilog_HDL_progamming
- Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.
BEIHANGVerilogjiaocheng
- 北航Verilog教程. Verilog HDL基本结构 数据类型及常量、变量 运算符及表达式 语句 赋值语句和块语句 条件语句 ... -BUAA Verilog Tutorial. Verilog HDL data types and the basic structure of constants, variables and expression operator assignment s
miaobiao
- 用Verilog HDL编写的秒表设计，可以实现百分之一秒，十分之一秒，秒，十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
alu
- 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181
Revised_Verilog_code
- 简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本-Honglun Jian, Revised Edition. Source coude of " Core Techniques of IC design"
uart
- uart using verilog hdl
hdl
- 双向RAM控制程序,使用VRILOG HDL 编写，简单实用-DAUL RAM control
I2C19861208888
- i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
verilog
- 中文版Verilog HDL简明教程，很简洁，结合实例，很容易理解，适合初学者。-Chinese version of Verilog HDL A simple tutorial, very simple, with an example, it is easy to understand for beginners.