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Four-serial-binary-adder
- 用Quartus II软件原理图编写四位串行二进制加法器-Principle of Quartus II software, written in four serial binary adder
Adder
- 加法器实现，让2个数实现计算器上的加法计算，计算完毕按clear键实现清除。-The adder achieve 2 the number of addition calculation on the calculator, the calculation is completed press the clear key to achieve clear.
4-bit-Ripple-Carry-adder
- it is 4 bit ripple carry adder. it is one type of counter you can say. in which carry is added. it is vhdl code and its waveform which is run in altera quars II.
adder-4
- 4 位加法器实现4个二进制位的相加 方便快捷-4-bit adder 4 binary bits adding quick and easy
Adder.java
- 用JAVA编写的关于加法器的小程序，很是经典的一个-Prepared using JAVA applet on the adder, it is one of the classic
Chapter15-Adder
- 书籍《精通Verilog HDL语言编程》中第15章的程序实例代码，是关于常用加法器的设计的，对于初学者有一定的帮助-Books "Proficient in Verilog HDL language programming" in Chapter 15 of the procedure code, common adder design have some help for beginners
adder
- 这是一个最简单的四位的全加器设计，由两个半加器构成，采用的是VERILOG的算法级和门级描述的。-This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descr iptions.
32-bit-cla-adder
- This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).
adder
- VHDL Adder implementation done in FPGA environment. VHDL Adder implementation done in FPGA environment.-VHDL Adder implementation done in FPGA environment.VHDL Adder implementation done in FPGA environment.VHDL Adder imp
ADDER
- 51单片机，加法器，包括键码扫描、储存、LED显示，有退格修改功能-51, adder, including key code scanning, storage, LED display, there is the backspace editing features
JAVA--Adder
- 可用于数字计算的小型加法器 使用JAVA语言编写-Can be used for digital computing small adder using JAVA language
Adder
- 加法器 实现加法运算 多线程 Java 的特点之一就是内置对多线程的支持-Adder adder multi-threaded implementation of Java features is built-in support for multithreading
adder
- 简单的加法运算,让初学者了解java的加法运算过程-Simple addition operations, allow beginners to understand the process of java adder
VHDL-CODE-for-adder-and-subtractor
- vhdl code for implementation of adder and subtractor on fpga
ADDER
- 超前进位加法器。时序好，功能可靠.工程引用已经验证。-Lookahead adder. Timing is good, functional and reliable
adder-8segmengt-display
- FPGA/CPLD开发，基于VHDL语言的加法器实现，并用数码管显示-FPGA/CPLD development, based on VHDL adder implementation, and use digital tube display
adder
- 加法器/计数器实例,该器程序主要实现加法器和计数功能。-Adder/Counter Instance
ADT-Adder-2.0
- adt adder for world of warcraft adt files
Adder
- Gate level implementation of two single bit Full Adder & Half Adder.
adder
- 二进制加法器流水灯，发上来给大家看看，互相学期吧-Binary adder water lights, made up for everyone to see, each semester,