搜索资源列表
adder
- 这是一个用VHDL语言描述的8位带符号加法器,希望对大家有用-This is a descr iption using VHDL, 8-bit adder with a symbol, we want to be useful
Adder
- GUI方法的浮点数加法器实例，运用了textfield和button-GUI method of floating-point adder instance, use the textfield and the button
fpufiles
- floating point adder mul and sub in verilog code
vhdl1
- vhdl program for 4 bit ripple carry adder using logic gates
vhdlcodes
- its VHDL coding for full adder and full substractor. 1.Structural model for Half Adder 2.Structural model for Full Adder 3.VHDL code for BEHAVIORAL model of Full Adder 4.VHDL CODE: full substractor (dataflow):
vhdlcodes1
- vhdl programs for 4 bit ripple carry adder in structural and behavioural modelling
quanjiaqi
- 建立了基于matlab语言的四位全加器仿真模型，通过了系统验证。-Matlab language is established based on four full adder simulation model, verified by the system.
adder
- 一位全加器,使用绘图方式,将2个半加器制成符号,供全加器调用,组合成全加器,方法简单易行,通过验证.-A full adder, using the drawing method will be made of two half adder symbol calls for the full adder, adder combination of sake, the method is simple and verified.
adder3
- 此源代码是基于Verilog语言的七人投票表决器 、2 个 8 位数相乘 、8 位二进制数的乘法 、同一循环的不同实现方式、使用了`include 语句的 16 位加法器 、条件编译、加法计数器中的进程、任务、测试、函数、用函数和 case语句描述的编码器、阶乘运算函数、测试程序 、顺序执行、并行执行，特别是七人投票表决器，这是我目前发现的最优的用硬件描述的源代码。-The Verilog language source code is
64B_adder
- Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
adder
- 一个最简单的加法器，带testbench-One of the most simple adder with testbench
Advanced_Adders
- Advanced topic on adders including: Carry Look Ahead Adder, Binary Parallel Adder/Subtractor, BCD adder circuit, Binary mutiplier circuit.
VLSI_Advanced_CSA
- Advanced VLSI Design on Carry Save Adder Implementation
cla16
- 16位超前进位加法器的源代码，整个工程文件都有，是在ISE10.1下建立的，可以帮助理解超前进位原理（对了，是Verilog的，因为上面没看到只好选VHDL了）-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead pri
adder_fa4bit
- 4 bit full adder verilog code n test bench
adder
- adder的程序代码！！希望需要的人下载！-adder of code! ! Hope that those who need to download! 11111
Adder_Kogge_Stone_32bit_With_Test_Bench
- verilog source code and test bench of Adder Kogge Stone 32-Bit
Full.adder
- Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
Gate.level.adder
- Verilog 门电路级别的全加器，测试通过-Verilog Gate Level adder and testbenck
16bit-CLA
- a 16 bit carry look ahead adder verilog code