搜索资源列表
FullAdder_4
- 这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。-This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder.
1_ADDER
- 使用硬件实现,通过FPGA验证的效率较高的加法器,-Realize the use of hardware, through the FPGA to verify the efficiency of higher adder,
ADD_Float_IEEE754
- IEEE754 floating point adder
5bit-adder-subtracter
- 5 bits 的加法器與減法器合併電路之原始程式製作 -5 bits of the adder circuit combined with the subtraction of the original browser program production
16szxgq
- 16位数字相关器，通过4个4位相关器和两级加法电路组成-16-bit digital correlator through four and four correlator adder circuit composed of two
fadder4
- VHDL实现四位全加器，适合初学者，源程序下载-VHDL realization of four full adder, suitable for beginners, the source code download
adder
- 此程序为用VERLOG HDL编写的一个完整的3位加法器。-This procedure for VERLOG HDL prepared with a full adder 3.
add_16_bcd
- 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 bina
add_32_bcd
- 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 bina
add2
- 两个4bit超前进位加法器实现8bit加法器-Two 4bit CLA realize 8bit adder
16_multi
- 16*16有符号乘法器的 编码方式：Booth编码， 拓扑结构：简单阵列 加法器：Ripple Carry Adder-16* 16 multiplier symbols have the
flowadd
- 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
cla_src
- carry lookahead adder verilog program
FULLADD
- Full adder using Verilog
VHDL
- 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
add
- 加法器 用VerilogHDL实现加罗华域加法器-Used realize adder VerilogHDL Le Hua domain adder
sd
- 自己做的数字逻辑电路课程设计，课题：八位二进制并行加法器的实现，包含代码和流程图以及基本说明-Themselves to do the digital logic circuit design, topics: 8 parallel binary adder realize that contains code and flow chart as well as basic instructions
work1ADD8
- 组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)
BINARY_ADD
- 算法类，二进制加法的源代码，算法导论上的-Algorithm-type, binary adder
fadd
- 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard