搜索资源列表
16bit-CLA
- 16 bit carry look ahead adder verilog code
adder
- 通过四个半加器的互联，来实现四位加法器的电路结构-Through the interconnection of four and a half adder to achieve the four adder circuit
csa1
- carry save adder block1
csa3
- carry save adder block3
Lookahead-adder
- 超前进位加法器，可以实现提前实现进位，加速算法。-Lookahead adder
adder
- adder 32 is very easy to use adder 32 is make up by 4 adder 4 and i have nothing to say already~!
Full-Adder
- Full Adder to add 4 bits of input
adder
- 加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。-The number of adder is produced and device. Addend and BeiJiaShu as input, and the device for output with binary for half a gal device. If BeiJiaSh
carry-ripple
- carry ripple adder code (whole project) in vhdl using xilinx tool. VHD file has source code
Lab-Sharp-4
- A full adder with non-uniform csa
serial-adder
- VHDL code for adding two hard-coded 8-bit binary numbers
serialadder
- serial adder in behavioural model
adder-VerilogHDL
- 各种加法器的VerilogHDL语言编写的包括普通加法器，串行进位加法器，超前进位加法器等-Adder VerilogHDL various languages, including ordinary adder, serial carry adder, CLA, etc.
ADDER
- 基于vhdl硬件描述语言设计的加法器电路 -Hardware descr iption language design based on vhdl adder circuit
digital-adder-source-code
- FPGA的Altera Quartus II 利用汇编语言实现加法器数码管的现实程序源代码-The Altera Quartus II FPGA using assembly language to achieve the reality of digital adder source code
hdl-hw1-brent-kung-adder
- BRENT KUNG ADDER 4 bits
cla-adder
- cla adder code in vhdl
Adder
- VHDL语言设计的加法器，在试验箱上使用8个拨码开关设置要加的2个数，按键按下输出相加的结果，在试验箱上测试通过。-Adder VHDL language design, in the chamber using the DIP switch setting 8 to 2 to add the number of keys pressed result of the addition output of the chamber on t
adder_32bits
- 32位进位选择加法器，预置逻辑0和逻辑1，各模块并行运行，只要通过进位位选择逻辑0或者逻辑1即可，提高了运行速度。-32-bit carry select adder, preset logic 0 and logic 1, the modules run in parallel, as long as through the carry bit selection logic 0 or logic 1 can improve the
adder
- 较好的加法器VHDL代码，大家需要可以下载，谢谢。-Better adder VHDL code, we need to download, thank you.