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ripple-lookahead-carryselect-adder
- Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple
counter&adder
- counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
fp-adder
- 上海交大float point adder 设计ppt-float point adder design ppt
fp-adder
- 上海交大float point adder 设计ppt-float point adder design ppt
jiajia
- 多位十进制数加法运算-number of decimal number Adder Operational
adder
- 加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
add_full_n
- 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.
小学生加法器设计
- java小应用程序开发，小学生加法器实现，包含友好界面，过程简洁，算法详细。-small application development, students achieve Adder, including friendly interface, simple process, the algorithm in detail.
booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers.
adder16bit
- 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行-16 high-speed adder using Verilog language has been successful simulation can be run
adderN
- N位加法器源代码，通用的，通过xilinx验证，希望对大家有用。-N-bit adder source code, a common, through Xilinx certification, useful for all.
vhdldesign
- 浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
counter&adder
- counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
2-bit-full-adder-master
- full adder 4 bit one you
Carry-Skip Adder
- 经典的进位跳跃、进位选择、并行前缀加法器，16位，基于verilog HDL语言(16-bit carry-skip adder)
Half-Adder
- This is an example to implement an Half-adder for xilinx FPGA
Half-Adder
- xilinx ISE平台提供1位半加法器，模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)
kogge stone adder VHDL code
- Generic kogge-stone adder and testbench IN VHDL
SPANNING TREE ADDER 27-bit VHDL
- 27-bit spanning tree adder written in VHDL coding
Adder
- VHDL code for 4bit adder and full/half adders