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FullAdderDesign
- This a design of Full Adder for DLD Students
VHDL
- VHDL. Realization of multi-digit adder
f_adder
- 一位加法全加器，可以实现低位进位输入和高位进位输出。-full adder
f_adder
- 用VHDL语言写的全加器，比较简单-Written in VHDL language with the full-adder
add
- VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
myjiafa
- 用函数语句实现的加法器-adder-function
u2
- fast carry adder using VHDL
ALUnew
- Half Adder which is implemented in gate level
VHDL
- A Full adder using half adder unit in vhdl
DISPLAYS_FINAL
- Program in VHDL. Developed for the spartan 3 kit. It is composed of 4-bit adder, with the result in the display board. It blocks the conversion of binary to BCD and multiplexed displays.
add32
- 一个32位超前进位加法器 不一样的算法 简单实用-An 32-bit look-ahead adder not the same as the algorithm
8-BT-ADDSUB
- efficient adder and subractor in FPGA
gatefullsub
- implementation of full adder
gui
- This a simple Adder!
Adder2
- This a simple adder-This is a simple adder!!
add_16bits
- 這是16bits加法器,利用verilog程式撰寫-adder-19bts
for_ws
- 裡頭有加法器,全加器,rippple adder-full adder ,rippple adder
fir_sine
- This implementation is moderately memory efficient because it stores only the first Pi/2 radians of sine values. The second Pi/2 radians is a mirror image of the first in time and the second Pi radians is a mirror image
Adder4
- 源码，内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder