搜索资源列表
crc_16
- CRC-16的编解码程序和仿真结果。统计了漏检概率随错误比特数目的曲线。-CRC-16 codec procedures and simulation results. Statistics of the undetected bit error probability with the number of curves.
2MovingVideoMonitorSystemBasedGPRS
- 本文主要研究了W-WAN中GPRS网络的移动视频传输问题。文中探讨了GPRS的网络结构、协议体系以及链路特性，从中我们看出： GPRS网络链路不仅具有一般无线链路数据传输中遇到的延迟大、误码率高等共性问题，而且具有移动通信系统采用蜂窝频率复用方式带来的小区切换， 以及由于通信中链路性能随着地理位置变换而变化造成的GPRS网络中不可避免的经常性遭遇的冗长时延和突变时延。 这使得目前GPRS网络中使用的传统TCP或UDP传输协议
crc
- 生成多项式的最高位必须是1。例如：CRC-CCITT标准的16位生成多项式：g（x）= x16+x12+x1+1；阶数r = 16 即：0x11021.最高位通常为1。-Generating polynomial must be the highest one. For example: CRC-CCITT standard 16-bit generation polynomial: g (x) = x16+ X12+ X1+ 1
MatlabBitPlaneDecomposition
- 该压缩包里包括了一幅图像的位平面解，即一幅灰度图像可以分成八个位平面。利用它可以转化到彩取色图像中去，很有用处的。-The bag includes a compressed image bit-plane solution, that is, a gray image can be divided into eight bit-plane. Use it can be transformed into the color check
Using_Linux_to_Implement_8-and16-BitDevice_Network
- Abstract: By using gateway systems on large 32-bit platforms, networks of small, 8- and 16-bit microcontrollers can be monitored and controlled over the Internet. With embedded Linux, these gateways are easily move
multipath
- 在matlab下实现多径信道仿真，计算误比特率-Matlab achieved in multi-path channel emulation, bit error rate calculation
FPGA_bit_clock_data_recovery
- 基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method
MAPAlgorithm
- This program includes: [5 7] convolutional code (encoder) + BPSK + AWGN + MAP (decoder). It evaluates Bit Error Rate and plots it versus SNR(signal to Noise Ratio). -This program includes: [5 7] convolutional code
Image_CompressionCoding
- 各类图像压缩编码的VC++综合程序，包含了霍夫曼编码、香农－费诺编码、算术编码、游程编码、位平面编码等压缩编码的子程序源代码，非常适合学习用-Various types of image compression coding VC++ Comprehensive program, including the Huffman coding, Shannon- Fenno coding, arithmetic coding, run-len
RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
Bmp24To16
- 将24位位图格式转换为16位位图格式的源代码，包括RGB555格式和RGB565格式。-24 will be converted to bitmap format 16-bit bitmap format source code, including the RGB555 and RGB565 format format.
buffervhdl
- 电子EDA,VHDL语言设计8位的fifo数据缓冲器的vhdl源程序-E-EDA, VHDL language design 8-bit data buffer fifo VHDL source code
lsb
- 利用LSB算法嵌入隐藏图像，可在广义LSB中设置修改的位平面，返回误码率和峰值信噪比。含各种经典的攻击方式，可用于实验。并可控制攻击的强弱。利用Matlab编写。-LSB embedding algorithm using hidden images, can be generalized to set up modified LSB bit-plane and returned to the bit error rate and pe
STDM
- 利用STDM方法嵌入水印信息，可设置量化步长，选择各种经典的攻击方式，控制攻击强弱，返回误码率和峰值信噪比-Stdm method using embedded watermark information, to set the quantization step size, choose a variety of classic attacks, controlling the strength of the attack and r
shift8
- 8 位移位寄存器 VHDL程序 VHDL程序 VHDL程序-8-bit shift register VHDL procedures VHDL procedures VHDL procedures
BFSK
- 准确的通信工程里的BFSK调制方式的性能仿真。给出了误码率和信噪比等参数。-Accurate communication engineering in the BFSK modulation of performance simulation. Given bit error rate and signal to noise ratio and other parameters.
lsbhide
- LSB隐藏 最低有效位隐藏算法,就是8:1嵌入-Least significant bit LSB hide hiding algorithm is embedded 8:1
crc8
- 8位crc校验算法，用于单片机编程，包含简单算法和查表算法-8-bit CRC checksum algorithm for single-chip programming, including a simple algorithm and look-up table algorithm
div2
- 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit dec
xu
- 序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器 -Sequence generator, producing an 8-bit serial number, serial code can be customized to amend, there is a sequence detector