搜索资源列表
bmp2c
- 将bmp文件转成16位彩色的C数组，用于生成WinCE启动画面需要的数据，用C#开发。还可以将生成好的C数组读入显示-Bmp files will be converted into 16-bit color of the C array, WinCE startup screen used to generate the data needed, and C# Development. Can also generate a good
shifter
- 8位双向移位寄存器: 实现串行数据与并行数据的转换,移位寄存数据功能的-8-bit bi-directional shift register: the realization of serial data and parallel data conversion, data storage function of displacement
16cpu
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the documen
OFDMmatlab
- ofdm程序，可以计算BER误码率，适合于入门-OFDM procedures, can calculate the BER bit error rate, suitable for entry-
multi_wavelet
- multi_wavelet An Image Digital Watermarking Algorithm Based on Bit-Plane-Decomposition and Multi-Resolution-Decomposition -multi_waveletAn Image Digital Watermarking Algorithm Based on Bit-Plane-Decomposition an
MUL32B
- 两个32位无符号整数的乘积的汇编程序 注意乘法的错位相加-Two 32-bit unsigned integer the product of the compilation process of dislocation multiplication sum attention
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
Programming
- \Programming 32-bit microcontrollers in C Microchip官方出的学习使用PIC32系列单片机的书 英文版-Programming 32-bit microcontrollers in C Microchip official of learning to use a PIC32 MCU books in English
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
Quartus7.2
- 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
aes_vb
- 一个类化的完整的AES实现方案.包含128Bit 256 Bit.不同的加密强度的完整的AES算法.同时也是一个成型的程序.可以用来直接加密需要保护的文件.-A class of a complete program of AES realize. Contains 128Bit 256 Bit. Different encryption strength of a complete AES algorithm. It is also
code
- 一个8位微处理器的VHDL代码以及testbench-8-bit processor VHDL
fpgafft
- :文章针对目前数字信号处理中大量采用的快速傅立叶变换[FFT] 算法采用软件编程来处理的应用现状,在对FFT 算法进行 分析的基础上,给出了用FPGA[Field Programmable Gate Array] 实现的8 点32 位FFT 处理器方案,并得到了系统的仿真结果。 最后在Altera 公司FLEX10K系列FPGA 芯片上成功地实现了综合。-Based on the analysis of the FFT algo
Bicm_8DPSK_Clip
- 在衰落信道下8DPSK的比特交织调制的维特比译码-Bit interleaved 8DPSK differentially coded modulation over Ricean fading channels and impulse noise environment
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX se
ber
- Bit error probability curve for QPSK mimo 1*2, Bit error probability curve for QPSK mimo 1*4-Bit error probability curve for QPSK mimo 1*2, Bit error probability curve for QPSK mimo 1*4
matlab_code_glonass
- forming of a signal, GLONASS system, coherent reception, graph autocorrelation, crosscorrelation function, bit-error probability[SNR]
QPSK
- 提出了一个采用(2,1,7)卷积码+QPSK的中频调制解调方案,并在Xilinx公司的100万 门FPGA芯片上实现了该系统。该系统在信噪比SNR为6dB左右时可实现速率超过1Mbit/s、误码率 小于10-5的数据传输。 -Proposed a use of (2,1,7) convolutional code+ QPSK modulation and demodulation of the IF program, and
ber
- bit Error Rate in Wireless communication
bit-error-rate_simulation_using_matlab
- Bit-Error-Rate Simulation Using Matlab