搜索资源列表
floatmul
- 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
interleaving.code
- 含有交织码编码与解码，以及纠错和误码率分析。-Containing intertwined code encoding and decoding, as well as error correction and bit error rate analysis.
ADC1
- 用FPGA实现的ADC采样器，用VHDL编写，8个模拟信号通道地址,8位数据输出-Using FPGA to achieve the ADC sampler, using VHDL prepared 8-channel analog signal address, 8-bit data output
add_16_bcd
- 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 bina
add_32_bcd
- 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 bina
OFDM
- matlab仿真ofdm系统以及误码率分析-matlab simulation of OFDM systems, as well as bit error rate analysis
1024FFT
- 一个基-2对时间抽取的1024点的快速傅立叶C语言算法,位倒序输入--2 For a time-based samples of 1024 points Fast Fourier C language algorithm, bit reverse input
8bit_cample
- 这是用数据流来设计的8位比较器,很简单,也很使用,希望能有所帮助,谢谢批评指导-This is used to design data stream 8-bit comparators, is simple and the use of, hoping to be helpful, thank you criticize guidance
4psk
- 4psk信号的蒙特卡洛误码率仿真，与理论误码率的对比-Monte Carlo signal 4psk BER simulation, and theoretical bit error rate comparison
MulPar
- 八位乘法器VHDL语言实现。使用的工具的ISE7.1，实现八乘八的位相乘。-8 Multiplier VHDL language. Tools used ISE7.1, realize eight by eight-bit multiplication.
ofdm1
- 这个源码能够对ofdm系统进行仿真，得出仿真结果，计算误码率-This source can OFDM system simulation, simulation results obtained to calculate the bit error rate
spiht3
- SPIHT方法采用了有效的空间方向树结构和比特平面编码方法，不仅能获得很高的压缩编码效率，而且产生的码流是嵌入式的，支持解码器的多码率解码，有利于图像的渐近传输。-Methods SPIHT effective direction of the tree structure and the space bit-plane coding method, not only have access to a high coding effic
cisc8bitCPU
- 一个用硬件描述语言编写的cisc类型8位总线长度cpu实例的源代码-A hardware descr iption language using the CISC type 8-bit bus the length of the source code examples cpu
ofdm_gito
- ofdm整个系统的详细仿真，内含误码率计算，输入输出信号频谱比较，星座点的分布-OFDM detailed simulation of the entire system, including bit error rate calculation, input and output signal spectrum of comparison, the distribution of constellation points
8-cpu
- 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc-8-bit CPU of the VHDL design, 16 instruction, as well as some of the test code, development tools is quartusii_60_pc
multiply
- 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
i2c_plib_examples
- Microchip的32位机PIC32的I2C通信范例程序，开发板是Explorer16，IC型号是PIC32MX360F512L.-Microchip s 32-bit machine PIC32 example of the I2C communication procedures, development board is Explorer16, IC model is PIC32MX360F512L.
RiscCPU8
- 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
chengxu
- 数字信号的传输：1、实现滚降系数分别为0，0.5，1时信号时域频域和功率谱密度以及眼图的波形，并比较异同。 2、对(2/4/8)PSK,DPSK通信系统进行蒙特卡罗仿真，通过功率谱密度、误比特率来比较他们的性能(采用最佳接收方式)。 -Digital signal transmission: 1, to achieve roll-off coefficients were 0,0.5,1 time domain when the
risc_cpu
- 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules