搜索资源列表
RISC_Core
- 这是用VerilogHDL描述的一个8位精简指令集处理器,包含完整代码,各种文档,以及测试环境。-This is described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.
multi8x8
- 实现了VHDL乘法器,8位乘法操作的完成-VHDL realize a multiplier, an 8-bit multiplication operation completed
MonteCarlo
- 二进制通信系统的进行蒙特卡罗仿真程序,以正交信号为基础。当均值分别等于0,0.1,1.0,2.0时完成10000个比特的仿真并求出误差概率。绘出理论误码率和蒙特拉罗仿真的差错率并进行比较这俩个结果,并绘出每个均值情况下判决器的1000个接受信噪比抽样-Binary communication systems to carry out Monte-Carlo simulation procedures to orthogonal sign
ber
- 模拟直扩系统中加性高斯白噪声信道环境下接受机误码率的计算-DS simulation system additive white Gaussian noise channel environment sets the bit error rate calculation
8-bit(PWM)
- 8位定时器H1(PWM 输出) -8-bit timer H1 (PWM output)
cpuinfo
- 获取cpu信息的源码,vc++实现的, 可以获取16位 和32位的cpu的信息, 而且源码文家独立给出-Cpu access to source information, vc++ Realize, you can access 16-bit and 32-bit cpu information, and independent source text is given
REG32
- 32位寄存器的VHDL的原代码下载,COOLCOOLCOOL-32-bit register of the original VHDL code download, COOLCOOLCOOL
mul_booth
- 基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source
adpcm
- 8位无符号4-BIT ADPCM编码和解码程序-8-bit unsigned 4-BIT ADPCM encoding and decoding procedures
work1ADD8
- 组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)
Signed32MultiplierV101
- 32位元2進位SIGNED乘法器32位元SIGNED乘法器-32-bit 2 binary SIGNED Multiplier Multiplier 32-bit SIGNED
32divider
- 32位元2進位除法器 -32-bit binary divider 2
Sample-16bit_to_32bit
- 16位与32位整数转换 整数正负反转 基偶数判断-16-bit and 32-bit integer integer conversion base even to determine positive and negative inversion
PSK8
- 关于8PSK解的信噪比和调误码率的仿真程序-8PSK solution on the signal to noise ratio and bit error rate of transfer simulation program
verilog_risc
- RISC状态机由三个功能单元构成:处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数,求16个数的和,放在数据存储器的16、17的位置,高位在前 对这16个数进行排序,从大到小放置在18到33的位置 求出前16个数的平均数,放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR
2psk_matlab
- 2psk的调制以及误码率等系统性能比较,里面分为好几个子程序更利于理解编写。-2psk modulation, as well as systems such as bit error rate performance comparison, which is divided into several more conducive to understanding the preparation of subprogram.
adder_32
- 超前进位加法器是通常数字设计所必备的,本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
32-bit_multiplier_model
- 此程序为32-bit乘法器,另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
alu_16
- 三种16位整数运算器的ALU设计方法,调用库函数74181(4位ALU),组成串行16位运算器。(用74181的正逻辑) B.调用库函数74181和74182,组成提前进位16位运算器。(用74181的正逻辑) 注意:调74181库设计,加进位是“0”有效,减借位是“1”有效,所以最高位进位或借位标志寄存器要统一调整到高有效 C.用always @,case方式描述16位运算器。-Three 16-bit integer
BICUSTM
- 一种比特交织编码调制,使用维特比译码。并给出误比特率曲线。-A Bit-Interleaved Coded Modulation, the use of Viterbi. Given bit error rate curve.