搜索资源列表
flowled
- FPGA开发入门的Verilog HDL程序---流水灯,真实可用,验证通过,工程环境为Altera Quartus
liangzhu
- FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用,验证通过,工程环境为Altera Quartus II
magnetic_stepping_motor_control_system
- 步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过
FPGA读写控制sram
- 拨码开关控制读写,按键控制地址加,读出数据由数码管显示,直观展现了程序是否正确。
通过 SPI 接口控制 I2C总线上音频器件数据流
用cycloneII的C020芯片来控制SPI转I2C的Verilog HDL程序
verilog HDL FFT程序
- 采用的verilog HDL语言编写的FFT的程序
someccode
- 一些c程序,象棋之马踏棋盘、把算术表达式转化未逆波兰表达式、保龄球计分规则算法、可进行多达50位的大整数运算(+X)、铁路调度算法,演示了堆栈的基本用法-Some c procedures, horse riding chess board, the arithmetic expressions are not translated into Reverse Polish expression, bowling scoring rule
pinglvhecheng
- 程序用VHDL实现: 频率合成,DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
ddsall
- DDS的vhdl语言源程序实现 该程序可实现1HZ频率步进-DDS source VHDL language to achieve the program can be realized 1HZ frequency Step
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
HDLDumpCmd
- PS2游戏硬盘直灌(HDL)的Windows下VC的源代码,根据HDUMP修改的(改正了几处错误)。命令行方式执行,具体使用说明可在命令行中看到。HDP.exe是执行程序。-PS2 drive straight Irrigation (HDL) VC Windows source code According HDUMP amended (corrected several errors). Command-line approach
veriloghdl快速入门
- verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware descr iption language procedures
scu_all_fpga
- 大型嵌入式设备FPGA程序,verilog HDL语言,实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
sram
- sram 读写小程序,用verilog编写的,请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
VerilogHDLPLI
- Verilog HDL的PLI子程序接口,用于与用户C程序在2个方向上传输数据,可用xilinx ISE,quartusii或modelsim仿真,-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii
dpram_fpga
- 这是我用vhdl语言,在fpga内部做了一个双口ram的程序。我的邮箱:wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
2006-9-21PanWeicaiDDS
- 这是一个DDS程序,用VHDL编写,实现的是一个频率可调的方波-This is a DDS procedures, using VHDL prepared achieve is a frequency adjustable square
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序,主要用于测频率,特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time
45668524655455
- 基于PID的介绍及实现,程序编写等自动温度控制-PID-based presentation and realized, programmers and other automatic temperature control