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- Verilog HDL程序设计与实践，从入门到提高，必备的资料-Verilog HDL program design and practice, from entry to the improvement of the information necessary
tlc549verilog
- tlc549的verilog HDL程序，希望对大家有用-tlc549 the verilog HDL program, we hope to be useful
hdl
- actel单片机的软FIFO设计和串口通讯程序-actel single chip design soft FIFO and serial communication program
3-8translater
- 3-8译码器的verilog hdl程序，实现3-8译码功能-3-8 decoder verilog hdl procedures to achieve decoding functions 3-8
I2C
- 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：model
UART
- FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
music
- 通过按键操作使峰鸣器发出乐器声的Verilog HDL程序-Through key operation so that buzzer sound instruments issued by Verilog HDL program
UART
- Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
HDL
- Vrilog HDL 语言设计的关于自动售货机的程序论文，详细精简，功能实现的效果很好-Vrilog HDL language design process on paper vending machine, more streamlined, functional to achieve good results
scdma_0.1
- 专网，SCDMA的FPGA同步控制verilog hdl程序-Special network, SCDMA' s FPGA synchronization process verilog hdl
Verilog-HDL-standard
- VERILOG的编码设计规范，使你的程序容易被理解，阅读和维护-VERILOG coding design specifications, to make your program easier to understand, read and maintain
Verilog-HDL
- Verilog HDL设计的示例程序与讲解
PLL
- 该测试程序用过Verilog HDL实现对PLL的分频，既频率管理功能-The Verilog HDL test procedure used to achieve the sub PLL frequency, only the frequency management function
VerilogPHDL
- Verilog+HDL程序设计实例详解10-13.rar，是学习velilog语言的好材料-Verilog+ HDL programming examples Detailed 10-13.rar, is a good material for language learning velilog
20110126113917873
- A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
LVDS-application-Verilog-HDL-code
- LVDS的应用的Verilog HDL例子程序-LVDS example of the application procedures for the Verilog HDL
And-serial-converter
- 实现1024位并行输入，32位串行输出的verilog HDL程序 并带有其测试程序-Achieve 1024 parallel input, 32-bit serial output verilog HDL program and with the test procedures and serial converter
sheji
- 伪随机码发射verilog HDL程序 大学生电子竞赛-Pseudo-random code transmitter verilog HDL program Undergraduate Electronic Contest
wangjinming-Verilog100
- 王金明：《Verilog HDL 程序设计教程》verilog 100例-Wang Jinming: "Verilog HDL programming tutorial" verilog 100 examples
VerilogHDL
- 王金明：《Verilog HDL 程序设计教程》-Verilog HDL