搜索资源列表
URAT_VHDL
- URAT VHDL程序与仿真 各程序运行环境为MAXPLUS_-UART procedures and VHDL simulation environment for the operation of the procedures for MAXPLUS_
dcm
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
binary_to_bcd.tar
- binary_to_bcd is used for translating from binare to bcd.-binary_to_bcd is used for translating fro m binare to bcd.
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
ASK.VHDL
- ASK调制VHDL程序及仿真 基于VHDL硬件描述语言，对基带信号进行ASK振幅调制-ASK modulation VHDL simulation based on the procedures and VHDL hardware descr iption language, the baseband signal amplitude modulation ASK
eepromVerilog24c32code
- eepromVerilog24c32code并带有文档资料-eepromVerilog24c32code with documents and information
vhdl_fifo
- 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
user_logic_VGA_Controller
- user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added dire
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
tcm8psk
- 本人编写的TCM解调源程序共享，为大家研究做简单的抛砖引玉-I prepared TCM demodulation source sharing, for everyone to consider doing something simple
CRC32_VHDL_SOURCE_CODE
- 这是利用VHDL编写的一个CRC32的代码，文档只有代码，具体原理请参考其他文献-This is the use of VHDL prepared a CRC32-code, the document is only a code Please refer to specific tenets of other literature
DCT_vhdl
- IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesi
Shifters_vhdl
- -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft licen
CRC_VHDL
- 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the ne
cordic
- 用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code
alu_32_bit
- verilog 32-bit ALU-verilog 32-bit ALU
20060411131929393
- SOURCE INSIGHT的VHDL语法插件，SOURCE INSIGHT支持自动完成等功能，是一个不错的硬件语言编辑分析器-SOURCE INSIGHT VHDL syntax plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers
IP_SPI
- spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
leon2-1[1].0.2a
- leon微处理器源代码，航空专用，功能强劲。包括详细说明-leon microprocessor source code, air flow, a strong function. Include a detailed descr iption of
bioviewer-0.0.21
- A C++/SDL/OpenGL player for the Biovision .bvh file format, which stores hierarchical motion data commonly originating from motion capture hardware. Support for the Kaydara .fbx format (a general 3D interchange format) i