搜索资源列表
SoCWishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
Wishboneandusb
- Wishbone 和 USB总线结构的介绍-Wishbone and the introduction of USB bus architecture
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
spi_wishbone
- spi wishbone bus code
wishbone_VHDL
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of
uart
- uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
ethernet.tar
- VHDL MAC wishbone VHDL MAC wishbone-VHDL MACVHDL MAC wishbone VHDL MAC wishbone
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
wb_lpc_latest.tar
- Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial
pit_latest.tar
- Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数
SDCard_Controller
- SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
pci.tar
- verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independe
spi_master
- SPI wishbone master and verification environment
wishbone_bus_protocol
- 是一份介绍wishbone总线非常好的资料，讲的很详细，希望对大家有帮助！-This is a very good introductory information about wishbone bus , speak in great detail, I hope it is a help to all of you!
wb_dma
- wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发-dma controller with wishbone interface，fitting for soc design，especially for video development.
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
ethmac_latest[1].tar
- 10M/100M 以太网mac，wishbone接口，可以直接使用-10M/100M Ethernet mac, wishbone interface, you can directly use
wb-ddr
- 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.