搜索资源列表
wbspec_b3
- soc中ip核集成时所采用的一种片上总线，开发的，为opencores所采用，wishbone片上总线指南-were integrated ip nuclear adopted by an on-chip bus, development, for opencores using the on-chip bus wishbone Guide
wb_conbus.tar
- wishbone 源代码，opencore-wishbone source code, opencore
wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Ose
adma
- Wishbone dma ip core
wishbone
- wishbone接口的设计，在交换机和MAC之间建立wishbone接口-the wishbone interface design, wishbone interface between the switch and MAC
wishbone-slave-and-master-to-avalon-bus
- wishbone slave and master to avalon bus verilog
wishbone
- wishbone片上总线系统设计，实现基本的共享总线实例。并用modelsim进行仿真。-wishbone chip bus system design, to achieve the basic shared bus instance. And use modelsim simulation.
WISHBONE-Interconnect-Matrix-IP-CORE
- 来自opencores.org 开源IP 很好的资料，供大家学习-WISHBONE Interconnect Matrix IP CORE
Wishbone
- wishbone总线的一些研究，包括一些代码-wishbone verilog
wishbone-flash-
- wishbone总线的Flash闪存接口设计的相关资料-relevant information wishbone bus Flash memory interface design
wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义
wishbone-serial
- USB Wishbone-Serial adapter driver for Linux v2.13.6.
wishbone-serial
- USB Wishbone-Serial adapter driver.
wishbone
- gives back a datavector containing locations and angles of a double wishbone suspension
i2c_wishbone.tar
- verilog i2c master wishbone slave wrapper
wb_handler-1.0.1.tar
- wishbone ctrl for fgpa - wb handler
wb_counter-1.0.1.tar
- wishbone counter for fpga
miniuart-1.0.0.tar
- wishbone uart controller
natebege-0.2.0.tar
- wishbone vhdl config tool
double wishbone tests
- double wishbone tests