搜索资源列表
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the co
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制,支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Mak
verilog
- PCI/WISHBONE bridge Reference Design-PCI/WISHBONE bridge Reference Design
i2c_master_slave_core_latest.tar
- This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.
a_vhd_16550_uart_latest.tar
- A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses
cfi_ctrl_latest.tar
- 很好的 wishbone转CFI FLASH接口的源码,在INTERL的FLASH上已经调试通过-CFI FLASH CORE
wb_conbus_latest.tar
- 源代码关于Verilog语言的wishbone总线-VHDL,verilog is very good
wishbone_vip
- wishbone protocol verification tool
WishboneSpecification
- WISHBONE Bus specification
wb_tdm_tb
- test bench that qualifies an avalon slave to wishbone interface right through to the end component
sdcard_mass_storage_controller.tar
- latest sdcard_mass_storage_controller core from opencores.org wishbone bus
SPI
- Verilog编写的SPI程序,含英文原文档说明,很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface
pci_to_wb_latest[1].tar
- 该ip核实现了容量为16MB的、双字、可寻址存储镜像与wishbone总线的连接-This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI s
wb_to_amba_latest[1].tar
- ahb总线到wishbone总线的桥接器,包括一个testbench,该版本暂不支持burst操作-A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported
simple_spi_latest.tar
- - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代,2,3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II,230在ACEX LCELLs的-- Compatible with Motorola s SPI specificati
i2c
- WISHBONE revB.2 compliant I2C Master controller Top-leve
or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram,最小系统soc。包括片上ram的软件系统(C语言编写)都有。但下载者要使用此系统需要很多工具链,搞soc的应该都装好了。 绝对原创!用quartusII11.0在Altera DE2-115上验证通过,Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating
viterb_encoder_and_decoder_latest.tar
- Category: Arithmetic core Language: Verilog Development status: Mature Additional info: Design done, Specification done WishBone Compliant: No
sdcard.tar
- 最新的基于wishbone总线的sd卡控制器设计-Latest sd card controller design based on the wishbone bus
ahb2wishbone_latest.tar
- AHB to Wishbone memory interface VHDL source code