搜索资源列表
pci_bridge
- 基于WISHBONE的pci桥实现，包括功能模块和测试模块-Based on the pci bridge WISHBONE implementation, including functional modules and test modules
i2c_wb_wrapper_latest.tar
- I2C+Wishbone in VHDL
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
spi_v
- 基于wishbone总线的spi串口控制器-a spi compilant serial port controller based on wishbone on-chip bus
a_vhdl_8253_timer_latest.tar
- 一个用VHDL语言编写的8254定时器。具有一个同步处理器接口比异步的INTEL8254要好-A VHDL 8254 timer，uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two
spi_latest[1].tar
- serial peripheral interface master interface Wishbone compatible
yadmc_latest.tar
- 基于wishbone总线的sdram控制器-sdram control with wishbone interface
wishbone
- 基于matlab的suspension system 优化-adams suspension system optimization
wb_lcd
- 基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language
8
- 基于ADAMS的双横臂独立悬架的仿真分析及优化设计，作者：QQ 64134703 ，欢迎咨询-ADAMS-based double wishbone independent suspension of the simulation analysis and optimization design of: QQ 64134703, welcomed the Advisory
166
- 基于ADAMS的双横臂独立悬架的仿真,作者：QQ 64134703 ，电子毕业设计，欢迎咨询-ADAMS-based double wishbone independent suspension of the simulation, the author: QQ 64134703, e-graduate design, please consult
167
- 基于ADAMS的双横臂独立悬架的优化设计,作者：QQ 64134703 ，电子毕业设计，欢迎咨询-ADAMS-based double wishbone independent suspension of the optimal design of: QQ 64134703, e-graduate design, please consult
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine conn
zorro_to_wishbone_bridge_latest.tar
- This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at th
wbspec_b4.pdf
- Wishbone interface, for development of system on chip interfaces
ThesummaryofSoCOCB
- 随着以IP核复用为基础的SoC设计技术的发展，工业界及研究组织积极从事相关IP互联标准 方案的制定工作，从目前的研究和发展看，影响力较大的有IBM 公司的CoreConnect、ARM 公司的AMBA 和Silicore Corp公司的Wishbone。基于现有IP互联接口标准技术的发展现状，本文对这三种SoC总线技 术进行了详细介绍。-Along with the IP core reuse-based SoC desig
uart_16550
- UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-A UART that is compatible with the industry standard 16550D includes wrappers for the Wishbone and AMBA APB busses
wishbonecode
- Optimization of a Double Wishbone Suspension System
wbspec_b3
- opensource 社区 引入的IP 互连总线，wishbone总线，这个是whitepaper. -opensource community into the IP interconnect bus, wishbone bus, this is a whitepaper.