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simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral I
rs232_syscon_v
- This a state-machine driven rs232 serial port interface to a \"Wishbone\" // type of bus.-This a state-driven machine rs232 seria l port interface to a "Wishbone" / / type of bus.
wishbone_i2c_master_vhd
- WISHBONE revB2 compiant I2C master core
opencores_i2c_master
- i2c VHDL,能够实现I2C 用的是wishbone总线
Wishbone_from_opencores
- 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。
OptimizationofaDoubleWishboneSuspensionSystem
- This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Toolbox to optimize the design of a double wishbone suspension system.
SoC_WishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core
The_Analyse_And_Research_of_embeded_SoC_Bus
- 本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线，通过比较这些总线的特性及适用范围，展望了它们的发展前景。
wisbone_2_ahb.tar
- ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Descr iption ---- --
wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Up
wbspec_b3
- Introduce the wishbone bus .
1256894
- STW石器快速抢双叉脚本，要在巴克那记录，大家可以来-STW stone quick grab double wishbone scr ipt, it records in Barker, we can come to
ethernet_vhdl
- 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
eth_ocm_80_2
- ethernet wishbone interface
simple_spi.tar
- Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types
suanhenbi02
- 汽车悬架运动学仿真/双横臂悬架/可以自由下载-Kinematics Simulation of automotive suspension/double wishbone suspension/free download
pif2wb_latest.tar
- This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB
wbspec_b3
- wishbone接口的规范，wishbone是嵌入式系统中支持的通用接口标准之一-wishbone spec